#include <string>
#include <sstream>
+#include "arch/faults.hh"
#include "base/cprintf.hh"
#include "base/trace.hh"
-
-#include "arch/faults.hh"
+#include "config/the_isa.hh"
#include "cpu/exetrace.hh"
-#include "mem/request.hh"
-
-#include "cpu/inorder/inorder_dyn_inst.hh"
#include "cpu/inorder/cpu.hh"
+#include "cpu/inorder/inorder_dyn_inst.hh"
+#include "mem/request.hh"
using namespace std;
using namespace TheISA;
InOrderDynInst::InOrderDynInst(InOrderCPU *cpu,
InOrderThreadState *state,
InstSeqNum seq_num,
- unsigned tid,
+ ThreadID tid,
unsigned _asid)
: traceData(NULL), cpu(cpu)
{
{
fetchMemReq = NULL;
dataMemReq = NULL;
-
+ splitMemData = NULL;
+ split2ndAddr = 0;
+ split2ndAccess = false;
+ splitInst = false;
+ splitInstSked = false;
+ splitFinishCnt = 0;
+
effAddr = 0;
physEffAddr = 0;
// Update Instruction Count for this instruction
++instcount;
- if (instcount > 500) {
+ if (instcount > 100) {
fatal("Number of Active Instructions in CPU is too high. "
"(Not Dereferencing Ptrs. Correctly?)\n");
}
- DPRINTF(InOrderDynInst, "DynInst: [tid:%i] [sn:%lli] Instruction created. (active insts: %i)\n",
- threadNumber, seqNum, instcount);
+ DPRINTF(InOrderDynInst, "DynInst: [tid:%i] [sn:%lli] Instruction created."
+ " (active insts: %i)\n", threadNumber, seqNum, instcount);
+}
+
+void
+InOrderDynInst::resetInstCount()
+{
+ instcount = 0;
}
delete traceData;
}
+ if (splitMemData) {
+ delete [] splitMemData;
+ }
+
fault = NoFault;
--instcount;
deleteStages();
- DPRINTF(InOrderDynInst, "DynInst: [tid:%i] [sn:%lli] Instruction destroyed. (active insts: %i)\n",
- threadNumber, seqNum, instcount);
+ DPRINTF(InOrderDynInst, "DynInst: [tid:%i] [sn:%lli] Instruction destroyed"
+ " (active insts: %i)\n", threadNumber, seqNum, instcount);
}
void
return initiateAcc();
}
+
+#if FULL_SYSTEM
+
+Fault
+InOrderDynInst::hwrei()
+{
+ panic("InOrderDynInst: hwrei: unimplemented\n");
+ return NoFault;
+}
+
+
+void
+InOrderDynInst::trap(Fault fault)
+{
+ this->cpu->trap(fault, this->threadNumber);
+}
+
+
+bool
+InOrderDynInst::simPalCheck(int palFunc)
+{
+#if THE_ISA != ALPHA_ISA
+ panic("simPalCheck called, but PAL only exists in Alpha!\n");
+#endif
+ return this->cpu->simPalCheck(palFunc, this->threadNumber);
+}
+#else
void
InOrderDynInst::syscall(int64_t callnum)
{
cpu->syscall(callnum, this->threadNumber);
}
+#endif
void
InOrderDynInst::prefetch(Addr addr, unsigned flags)
while(list_it != list_end) {
if((*list_it)->getResIdx() == req->getResIdx() &&
(*list_it)->getSlot() == req->getSlot()) {
- DPRINTF(InOrderDynInst, "[tid:%u]: [sn:%i] Done with request to %s.\n",
- threadNumber, seqNum, req->res->name());
+ DPRINTF(InOrderDynInst, "[tid:%u]: [sn:%i] Done with request "
+ "to %s.\n", threadNumber, seqNum, req->res->name());
reqList.erase(list_it);
return;
}
void
InOrderDynInst::setIntSrc(int idx, uint64_t val)
{
- DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Source Value %i being set to %#x.\n",
- threadNumber, seqNum, idx, val);
+ DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Source Value %i being set "
+ "to %#x.\n", threadNumber, seqNum, idx, val);
instSrc[idx].integer = val;
}
/** Records an fp register being set to a value. */
void
-InOrderDynInst::setFloatSrc(int idx, FloatReg val, int width)
+InOrderDynInst::setFloatSrc(int idx, FloatReg val)
{
- if (width == 32)
- instSrc[idx].dbl = val;
- else if (width == 64)
- instSrc[idx].dbl = val;
- else
- panic("Unsupported width!");
+ instSrc[idx].dbl = val;
}
/** Records an fp register being set to an integer value. */
/** Reads a integer register. */
IntReg
-InOrderDynInst::readIntRegOperand(const StaticInst *si, int idx, unsigned tid)
+InOrderDynInst::readIntRegOperand(const StaticInst *si, int idx, ThreadID tid)
{
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Source Value %i read as %#x.\n",
threadNumber, seqNum, idx, instSrc[idx].integer);
/** Reads a FP register. */
FloatReg
-InOrderDynInst::readFloatRegOperand(const StaticInst *si, int idx, int width)
-{
- if (width == 32)
- return (float)instSrc[idx].dbl;
- else if (width == 64)
- return instSrc[idx].dbl;
- else {
- panic("Unsupported Floating Point Width!");
- return 0;
- }
+InOrderDynInst::readFloatRegOperand(const StaticInst *si, int idx)
+{
+ return instSrc[idx].dbl;
}
/** Reads a FP register as a integer. */
FloatRegBits
-InOrderDynInst::readFloatRegOperandBits(const StaticInst *si, int idx, int width)
+InOrderDynInst::readFloatRegOperandBits(const StaticInst *si, int idx)
{
return instSrc[idx].integer;
}
}
MiscReg
-InOrderDynInst::readRegOtherThread(unsigned reg_idx, int tid)
+InOrderDynInst::readRegOtherThread(unsigned reg_idx, ThreadID tid)
{
if (tid == -1) {
tid = TheISA::getTargetThread(this->cpu->tcBase(threadNumber));
instResult[idx].type = Integer;
instResult[idx].val.integer = val;
instResult[idx].tick = curTick;
+
+ DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Result Int Reg. %i "
+ "being set to %#x (result-tick:%i).\n",
+ threadNumber, seqNum, idx, val, instResult[idx].tick);
}
/** Sets a FP register. */
void
-InOrderDynInst::setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, int width)
-{
- if (width == 32) {
- instResult[idx].val.dbl = (float)val;
- instResult[idx].type = Float;
- } else if (width == 64) {
- instResult[idx].val.dbl = val;
- instResult[idx].type = Double;
- } else {
- panic("Unsupported Floating Point Width!");
- }
-
+InOrderDynInst::setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
+{
+ instResult[idx].val.dbl = val;
+ instResult[idx].type = Float;
instResult[idx].tick = curTick;
- instResult[idx].width = width;
+
+ DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Result Float Reg. %i "
+ "being set to %#x (result-tick:%i).\n",
+ threadNumber, seqNum, idx, val, instResult[idx].tick);
}
/** Sets a FP register as a integer. */
void
InOrderDynInst::setFloatRegOperandBits(const StaticInst *si, int idx,
- FloatRegBits val, int width)
+ FloatRegBits val)
{
instResult[idx].type = Integer;
instResult[idx].val.integer = val;
instResult[idx].tick = curTick;
- instResult[idx].width = width;
+
+ DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Result Float Reg. %i "
+ "being set to %#x (result-tick:%i).\n",
+ threadNumber, seqNum, idx, val, instResult[idx].tick);
}
/** Sets a misc. register. */
}
void
-InOrderDynInst::setRegOtherThread(unsigned reg_idx, const MiscReg &val, int tid)
+InOrderDynInst::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
+ ThreadID tid)
{
- if (tid == -1) {
+ if (tid == InvalidThreadID) {
tid = TheISA::getTargetThread(this->cpu->tcBase(threadNumber));
}
this->cpu->deallocateContext(thread_num);
}
-void
-InOrderDynInst::enableVirtProcElement(unsigned vpe)
-{
- this->cpu->enableVirtProcElement(vpe);
-}
-
-void
-InOrderDynInst::disableVirtProcElement(unsigned vpe)
-{
- this->cpu->disableVirtProcElement(threadNumber, vpe);
-}
-
-void
-InOrderDynInst::enableMultiThreading(unsigned vpe)
-{
- this->cpu->enableMultiThreading(vpe);
-}
-
-void
-InOrderDynInst::disableMultiThreading(unsigned vpe)
-{
- this->cpu->disableMultiThreading(threadNumber, vpe);
-}
-
template<class T>
inline Fault
InOrderDynInst::read(Addr addr, T &data, unsigned flags)
{
+ if (traceData) {
+ traceData->setAddr(addr);
+ traceData->setData(data);
+ }
+
return cpu->read(this, addr, data, flags);
}
inline Fault
InOrderDynInst::write(T data, Addr addr, unsigned flags, uint64_t *res)
{
- //memcpy(memData, gtoh(data), sizeof(T));
+ if (traceData) {
+ traceData->setAddr(addr);
+ traceData->setData(data);
+ }
+
storeData = data;
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting store data to %#x.\n",
- threadNumber, seqNum, memData);
+ threadNumber, seqNum, storeData);
return cpu->write(this, data, addr, flags, res);
}
return hash;
}
-typedef m5::hash_map<const InOrderDynInst *, const InOrderDynInst *, MyHashFunc>
+typedef m5::hash_map<const InOrderDynInst *, const InOrderDynInst *,
+ MyHashFunc>
my_hash_t;
my_hash_t thishash;
projects / gem5.git / blobdiff