#include <list>
#include <string>
+#include "arch/isa_traits.hh"
#include "arch/faults.hh"
+#include "arch/types.hh"
+#include "arch/mt.hh"
#include "base/fast_alloc.hh"
#include "base/trace.hh"
#include "cpu/inorder/inorder_trace.hh"
* @param cpu Pointer to the instruction's CPU.
* NOTE: Must set Binary Instrution through Member Function
*/
- InOrderDynInst(InOrderCPU *cpu, InOrderThreadState *state, InstSeqNum seq_num,
- unsigned tid);
+ InOrderDynInst(InOrderCPU *cpu, InOrderThreadState *state,
+ InstSeqNum seq_num, ThreadID tid, unsigned asid = 0);
/** BaseDynInst constructor given a StaticInst pointer.
* @param _staticInst The StaticInst for this BaseDynInst.
/** An instruction src/dest has to be one of these types */
union InstValue {
uint64_t integer;
- float fp;
double dbl;
};
+ //@TODO: Naming Convention for Enums?
+ enum ResultType {
+ None,
+ Integer,
+ Float,
+ Double
+ };
+
+
/** Result of an instruction execution */
struct InstResult {
+ ResultType type;
InstValue val;
Tick tick;
+ int width;
+
+ InstResult()
+ : type(None), tick(0), width(0)
+ {}
};
/** The source of the instruction; assumes for now that there's only one
/** Predicted next PC. */
Addr predPC;
+ /** Predicted next NPC. */
+ Addr predNPC;
+
+ /** Predicted next microPC */
+ Addr predMicroPC;
+
/** Address to fetch from */
Addr fetchAddr;
// BASE INSTRUCTION INFORMATION.
//
////////////////////////////////////////////////////////////
+ std::string instName() { return staticInst->getName(); }
+
+
void setMachInst(ExtMachInst inst);
/** Sets the StaticInst. */
short readTid() { return threadNumber; }
/** Sets the thread id. */
- void setTid(unsigned tid) { threadNumber = tid; }
+ void setTid(ThreadID tid) { threadNumber = tid; }
void setVpn(int id) { virtProcNumber = id; }
/** Print Resource Schedule */
+ /** @NOTE: DEBUG ONLY */
void printSched()
{
- using namespace ThePipeline;
-
- ResSchedule tempSched;
+ ThePipeline::ResSchedule tempSched;
std::cerr << "\tInst. Res. Schedule: ";
while (!resSched.empty()) {
std::cerr << '\t' << resSched.top()->stageNum << "-"
virtual void enableMultiThreading(unsigned vpe);
virtual void disableMultiThreading(unsigned vpe);
- virtual void setThreadRescheduleCondition(uint32_t cond);
-
////////////////////////////////////////////////////////////
//
// PROGRAM COUNTERS - PC/NPC/NPC
/** Returns the next NPC. This could be the speculative next NPC if it is
* called prior to the actual branch target being calculated.
*/
- Addr readNextNPC() { return nextNPC; }
+ Addr readNextNPC()
+ {
+#if ISA_HAS_DELAY_SLOT
+ return nextNPC;
+#else
+ return nextPC + sizeof(TheISA::MachInst);
+#endif
+ }
/** Set the next PC of this instruction (its actual target). */
void setNextNPC(uint64_t val) { nextNPC = val; }
/** Returns the predicted target of the branch. */
Addr readPredTarg() { return predPC; }
+ /** Returns the predicted PC immediately after the branch. */
+ Addr readPredPC() { return predPC; }
+
+ /** Returns the predicted PC two instructions after the branch */
+ Addr readPredNPC() { return predNPC; }
+
+ /** Returns the predicted micro PC after the branch */
+ Addr readPredMicroPC() { return predMicroPC; }
+
/** Returns whether the instruction was predicted taken or not. */
bool predTaken() { return predictTaken; }
/** Returns whether the instruction mispredicted. */
bool mispredicted()
{
- // Special case since a not-taken, cond. delay slot, effectively
- // nullifies the delay slot instruction
- if (isCondDelaySlot() && !predictTaken) {
- return predPC != nextPC;
- } else {
- return predPC != nextNPC;
- }
+#if ISA_HAS_DELAY_SLOT
+ return predPC != nextNPC;
+#else
+ return predPC != nextPC;
+#endif
}
/** Returns whether the instruction mispredicted. */
/** Read Effective Address from instruction & do memory access */
Fault memAccess();
- RequestPtr memReq;
+ RequestPtr fetchMemReq;
+ RequestPtr dataMemReq;
bool memAddrReady;
Addr getMemAddr()
{ return memAddr; }
- int getMemAccSize() { return staticInst->memAccSize(this); }
-
- int getMemFlags() { return staticInst->memAccFlags(); }
-
/** Sets the effective address. */
void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
* language (which is why the name isnt readIntSrc(...)) Note: That
* the source reg. value is set using the setSrcReg() function.
*/
- IntReg readIntRegOperand(const StaticInst *si, int idx, unsigned tid=0);
+ IntReg readIntRegOperand(const StaticInst *si, int idx, ThreadID tid = 0);
FloatReg readFloatRegOperand(const StaticInst *si, int idx,
int width = TheISA::SingleWidth);
- FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
+ TheISA::FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
int width = TheISA::SingleWidth);
MiscReg readMiscReg(int misc_reg);
MiscReg readMiscRegNoEffect(int misc_reg);
MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx);
/** Returns the result value instruction. */
- uint64_t readIntResult(int idx) { return instResult[idx].val.integer; }
- float readFloatResult(int idx) { return instResult[idx].val.fp; }
- double readDoubleResult(int idx) { return instResult[idx].val.dbl; }
+ ResultType resultType(int idx)
+ {
+ return instResult[idx].type;
+ }
+
+ uint64_t readIntResult(int idx)
+ {
+ return instResult[idx].val.integer;
+ }
+
+ /** Depending on type, return Float or Double */
+ double readFloatResult(int idx)
+ {
+ //Should this function have a parameter for what width of return?x
+ return (instResult[idx].type == Float) ?
+ (float) instResult[idx].val.dbl : instResult[idx].val.dbl;
+ }
+
+ double readDoubleResult(int idx)
+ {
+ assert(instResult[idx].type == Double);
+ return instResult[idx].val.dbl;
+ }
+
Tick readResultTime(int idx) { return instResult[idx].tick; }
uint64_t* getIntResultPtr(int idx) { return &instResult[idx].val.integer; }
void setIntRegOperand(const StaticInst *si, int idx, IntReg val);
void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
int width = TheISA::SingleWidth);
- void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val,
+ void setFloatRegOperandBits(const StaticInst *si, int idx, TheISA::FloatRegBits val,
int width = TheISA::SingleWidth);
void setMiscReg(int misc_reg, const MiscReg &val);
void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val);
void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val);
- virtual uint64_t readRegOtherThread(unsigned idx, int tid = -1);
- virtual void setRegOtherThread(unsigned idx, const uint64_t &val, int tid = -1);
+ virtual uint64_t readRegOtherThread(unsigned idx,
+ ThreadID tid = InvalidThreadID);
+ virtual void setRegOtherThread(unsigned idx, const uint64_t &val,
+ ThreadID tid = InvalidThreadID);
+
+ /** Sets the number of consecutive store conditional failures. */
+ void setStCondFailures(unsigned sc_failures)
+ { thread->storeCondFailures = sc_failures; }
//////////////////////////////////////////////////////////////
//
projects / gem5.git / blobdiff