MEM: Remove the Broadcast destination from the packet

[gem5.git] / src / cpu / inorder / inorder_dyn_inst.hh

diff --git a/src/cpu/inorder/inorder_dyn_inst.hh b/src/cpu/inorder/inorder_dyn_inst.hh
index b655de380b2418da361ad13c8775c2fc3abfb021..4b48a157b7c03bd58e5adbc3f6df354b8eb25adf 100644 (file)
--- a/src/cpu/inorder/inorder_dyn_inst.hh
+++ b/src/cpu/inorder/inorder_dyn_inst.hh
@@ -37,7 +37,6 @@
 #include <list>
 #include <string>
 
-#include "arch/faults.hh"
 #include "arch/isa_traits.hh"
 #include "arch/mt.hh"
 #include "arch/types.hh"
@@ -45,7 +44,6 @@
 #include "base/fast_alloc.hh"
 #include "base/trace.hh"
 #include "base/types.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "cpu/inorder/inorder_trace.hh"
 #include "cpu/inorder/pipeline_traits.hh"
@@ -59,6 +57,7 @@
 #include "cpu/thread_context.hh"
 #include "debug/InOrderDynInst.hh"
 #include "mem/packet.hh"
+#include "sim/fault_fwd.hh"
 #include "sim/system.hh"
 
 #if THE_ISA == ALPHA_ISA
@@ -71,7 +70,6 @@
  */
 
 // Forward declaration.
-class StaticInstPtr;
 class ResourceRequest;
 class Packet;
 
@@ -105,7 +103,7 @@ class InOrderDynInst : public FastAlloc, public RefCounted
 
     enum {
         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        /// Max source regs
-        MaxInstDestRegs = TheISA::MaxInstDestRegs,      /// Max dest regs
+        MaxInstDestRegs = TheISA::MaxInstDestRegs       /// Max dest regs
     };
 
   public:
@@ -324,7 +322,7 @@ class InOrderDynInst : public FastAlloc, public RefCounted
     std::string instName()
     { return (staticInst) ? staticInst->getName() : "undecoded-inst"; }
 
-    void setMachInst(ExtMachInst inst);
+    void setStaticInst(StaticInstPtr si);
 
     ExtMachInst getMachInst() { return staticInst->machInst; }
 
@@ -400,6 +398,8 @@ class InOrderDynInst : public FastAlloc, public RefCounted
     bool isUnverifiable() const { return staticInst->isUnverifiable(); }
     bool isSyscall() const
     { return staticInst->isSyscall(); }
+    bool isMicroop() const { return staticInst->isMicroop(); }
+    bool isLastMicroop() const { return staticInst->isLastMicroop(); }
 
 
     /////////////////////////////////////////////
@@ -518,18 +518,15 @@ class InOrderDynInst : public FastAlloc, public RefCounted
     void setCurResSlot(unsigned slot_num) { curResSlot = slot_num; }
 
     /** Calls a syscall. */
-#if FULL_SYSTEM
     /** Calls hardware return from error interrupt. */
     Fault hwrei();
     /** Traps to handle specified fault. */
     void trap(Fault fault);
     bool simPalCheck(int palFunc);
-#else
     short syscallNum;
 
-    /** Calls a syscall. */
+    /** Emulates a syscall. */
     void syscall(int64_t callnum);
-#endif
 
     ////////////////////////////////////////////////////////////
     //
@@ -612,32 +609,11 @@ class InOrderDynInst : public FastAlloc, public RefCounted
     // MEMORY ACCESS
     //
     ////////////////////////////////////////////
-    /**
-     * Does a read to a given address.
-     * @param addr The address to read.
-     * @param data The read's data is written into this parameter.
-     * @param flags The request's flags.
-     * @return Returns any fault due to the read.
-     */
-    template <class T>
-    Fault read(Addr addr, T &data, unsigned flags);
-
-    Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
-
-    /**
-     * Does a write to a given address.
-     * @param data The data to be written.
-     * @param addr The address to write to.
-     * @param flags The request's flags.
-     * @param res The result of the write (for load locked/store conditionals).
-     * @return Returns any fault due to the write.
-     */
-    template <class T>
-    Fault write(T data, Addr addr, unsigned flags,
-                        uint64_t *res);
 
-    Fault writeBytes(uint8_t *data, unsigned size,
-                     Addr addr, unsigned flags, uint64_t *res);
+    Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
+
+    Fault writeMem(uint8_t *data, unsigned size,
+                   Addr addr, unsigned flags, uint64_t *res);
 
     /** Initiates a memory access - Calculate Eff. Addr & Initiate Memory
      *  Access Only valid for memory operations.
@@ -867,7 +843,7 @@ class InOrderDynInst : public FastAlloc, public RefCounted
     void setFloatSrc(int idx, FloatReg val);
     void setFloatRegBitsSrc(int idx, TheISA::FloatRegBits val);
 
-    uint64_t* getIntSrcPtr(int idx) { return &instSrc[idx].intVal; }
+    TheISA::IntReg* getIntSrcPtr(int idx) { return &instSrc[idx].intVal; }
     uint64_t readIntSrc(int idx) { return instSrc[idx].intVal; }
 
     /** These Instructions read a integer/float/misc. source register
@@ -943,6 +919,9 @@ class InOrderDynInst : public FastAlloc, public RefCounted
     /** Sets this instruction as entered on the CPU Reg Dep Map */
     void setRegDepEntry() { status.set(RegDepMapEntry); }
 
+    /** Unsets this instruction as entered on the CPU Reg Dep Map */
+    void clearRegDepEntry() { status.reset(RegDepMapEntry); }
+
     /** Returns whether or not the entry is on the CPU Reg Dep Map */
     bool isRegDepEntry() const { return status[RegDepMapEntry]; }