#include "base/types.hh"
#include "config/full_system.hh"
#include "config/the_isa.hh"
-#include "cpu/exetrace.hh"
#include "cpu/inorder/inorder_trace.hh"
#include "cpu/inorder/pipeline_traits.hh"
#include "cpu/inorder/resource.hh"
#include "cpu/inorder/resource_sked.hh"
#include "cpu/inorder/thread_state.hh"
+#include "cpu/exetrace.hh"
#include "cpu/inst_seq.hh"
#include "cpu/op_class.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
+#include "debug/InOrderDynInst.hh"
#include "mem/packet.hh"
#include "sim/system.hh"
*/
// Forward declaration.
-class StaticInstPtr;
class ResourceRequest;
class Packet;
// Floating point register type.
typedef TheISA::FloatReg FloatReg;
// Floating point register type.
+ typedef TheISA::FloatRegBits FloatRegBits;
+ // Floating point register type.
typedef TheISA::MiscReg MiscReg;
typedef short int PhysRegIndex;
};
public:
- /** BaseDynInst constructor given a binary instruction.
- * @param inst The binary instruction.
- * @param PC The PC of the instruction.
- * @param predPC The predicted next PC.
- * @param seq_num The sequence number of the instruction.
- * @param cpu Pointer to the instruction's CPU.
- */
- InOrderDynInst(ExtMachInst inst, const TheISA::PCState &PC,
- const TheISA::PCState &predPC, InstSeqNum seq_num,
- InOrderCPU *cpu);
-
/** BaseDynInst constructor given a binary instruction.
* @param seq_num The sequence number of the instruction.
* @param cpu Pointer to the instruction's CPU.
InOrderDynInst(InOrderCPU *cpu, InOrderThreadState *state,
InstSeqNum seq_num, ThreadID tid, unsigned asid = 0);
- /** BaseDynInst constructor given a StaticInst pointer.
- * @param _staticInst The StaticInst for this BaseDynInst.
- */
- InOrderDynInst(StaticInstPtr &_staticInst);
-
- /** Skeleton Constructor. */
- InOrderDynInst();
-
/** InOrderDynInst destructor. */
~InOrderDynInst();
/** The sequence number of the instruction. */
InstSeqNum seqNum;
- /** The sequence number of the instruction. */
- InstSeqNum bdelaySeqNum;
+ /** If this instruction is squashing, the number should we squash behind. */
+ InstSeqNum squashSeqNum;
enum Status {
RegDepMapEntry, /// Instruction is entered onto the RegDepMap
/** The effective physical address. */
Addr physEffAddr;
- /** Effective virtual address for a copy source. */
- Addr copySrcEffAddr;
-
- /** Effective physical address for a copy source. */
- Addr copySrcPhysEffAddr;
-
/** The memory request flags (from translation). */
unsigned memReqFlags;
/** How many source registers are ready. */
unsigned readyRegs;
- /** An instruction src/dest has to be one of these types */
- union InstValue {
- uint64_t integer;
- double dbl;
- };
-
- //@TODO: Naming Convention for Enums?
enum ResultType {
None,
Integer,
Float,
+ FloatBits,
Double
};
+ /** An instruction src/dest has to be one of these types */
+ struct InstValue {
+ IntReg intVal;
+ union {
+ FloatReg f;
+ FloatRegBits i;
+ } fpVal;
+
+ InstValue()
+ {
+ intVal = 0;
+ fpVal.i = 0;
+ }
+ };
/** Result of an instruction execution */
struct InstResult {
ResultType type;
- InstValue val;
+ InstValue res;
Tick tick;
InstResult()
- : type(None), tick(0)
- {}
+ : type(None), tick(0)
+ { }
};
/** The source of the instruction; assumes for now that there's only one
/** Predicted next PC. */
TheISA::PCState predPC;
- /** Address to fetch from */
- Addr fetchAddr;
-
/** Address to get/write data from/to */
+ /* Fetching address when inst. starts, Data address for load/store after fetch*/
Addr memAddr;
/** Whether or not the source register is ready.
*/
bool _readySrcRegIdx[MaxInstSrcRegs];
+ /** Flattened register index of the destination registers of this
+ * instruction.
+ */
+ TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
+
+ /** Flattened register index of the source registers of this
+ * instruction.
+ */
+ TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs];
+
/** Physical register index of the destination registers of this
* instruction.
*/
// BASE INSTRUCTION INFORMATION.
//
////////////////////////////////////////////////////////////
- std::string instName() { return staticInst->getName(); }
+ std::string instName()
+ { return (staticInst) ? staticInst->getName() : "undecoded-inst"; }
- void setMachInst(ExtMachInst inst);
+ void setStaticInst(StaticInstPtr si);
ExtMachInst getMachInst() { return staticInst->machInst; }
/** Returns the fault type. */
Fault getFault() { return fault; }
+ /** Read this CPU's ID. */
+ int cpuId();
+
+ /** Read this context's system-wide ID **/
+ int contextId() { return thread->contextId(); }
+
////////////////////////////////////////////////////////////
//
// INSTRUCTION TYPES - Forward checks to StaticInst object.
{ return staticInst->isStoreConditional(); }
bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
- bool isCopy() const { return staticInst->isCopy(); }
bool isInteger() const { return staticInst->isInteger(); }
bool isFloating() const { return staticInst->isFloating(); }
bool isControl() const { return staticInst->isControl(); }
bool isQuiesce() const { return staticInst->isQuiesce(); }
bool isIprAccess() const { return staticInst->isIprAccess(); }
bool isUnverifiable() const { return staticInst->isUnverifiable(); }
+ bool isSyscall() const
+ { return staticInst->isSyscall(); }
+
/////////////////////////////////////////////
//
curSkedEntry++;
if (inFrontEnd && curSkedEntry == frontSked_end) {
- assert(backSked != NULL);
- curSkedEntry.init(backSked);
- curSkedEntry = backSked->begin();
- inFrontEnd = false;
+ DPRINTF(InOrderDynInst, "[sn:%i] Switching to "
+ "back end schedule.\n", seqNum);
+ assert(backSked != NULL);
+ curSkedEntry.init(backSked);
+ curSkedEntry = backSked->begin();
+ inFrontEnd = false;
} else if (!inFrontEnd && curSkedEntry == backSked_end) {
return true;
}
+ DPRINTF(InOrderDynInst, "[sn:%i] Next Stage: %i "
+ "Next Resource: %i.\n", seqNum, curSkedEntry->stageNum,
+ curSkedEntry->resNum);
+
return false;
}
void trap(Fault fault);
bool simPalCheck(int palFunc);
#else
- /** Calls a syscall. */
- void syscall(int64_t callnum);
+ short syscallNum;
#endif
+ /** Emulates a syscall. */
+ void syscall(int64_t callnum);
+
////////////////////////////////////////////////////////////
//
// MULTITHREADING INTERFACE TO CPU MODELS
bool procDelaySlotOnMispred;
+ void setSquashInfo(unsigned stage_num);
+
////////////////////////////////////////////
//
// MEMORY ACCESS
//
////////////////////////////////////////////
- /**
- * Does a read to a given address.
- * @param addr The address to read.
- * @param data The read's data is written into this parameter.
- * @param flags The request's flags.
- * @return Returns any fault due to the read.
- */
- template <class T>
- Fault read(Addr addr, T &data, unsigned flags);
-
- Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
-
- /**
- * Does a write to a given address.
- * @param data The data to be written.
- * @param addr The address to write to.
- * @param flags The request's flags.
- * @param res The result of the write (for load locked/store conditionals).
- * @return Returns any fault due to the write.
- */
- template <class T>
- Fault write(T data, Addr addr, unsigned flags,
- uint64_t *res);
- Fault writeBytes(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res);
+ Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
+
+ Fault writeMem(uint8_t *data, unsigned size,
+ Addr addr, unsigned flags, uint64_t *res);
/** Initiates a memory access - Calculate Eff. Addr & Initiate Memory
* Access Only valid for memory operations.
return _srcRegIdx[idx];
}
+ /** Flattens a source architectural register index into a logical index.
+ */
+ void flattenSrcReg(int idx, TheISA::RegIndex flattened_src)
+ {
+ _flatSrcRegIdx[idx] = flattened_src;
+ }
+
+ /** Flattens a destination architectural register index into a logical
+ * index.
+ */
+ void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
+ {
+ _flatDestRegIdx[idx] = flattened_dest;
+ }
+
+ /** Returns the flattened register index of the i'th destination
+ * register.
+ */
+ TheISA::RegIndex flattenedDestRegIdx(int idx) const
+ {
+ return _flatDestRegIdx[idx];
+ }
+
+ /** Returns the flattened register index of the i'th source register */
+ TheISA::RegIndex flattenedSrcRegIdx(int idx) const
+ {
+ return _flatSrcRegIdx[idx];
+ }
+
/** Returns the physical register index of the previous physical register
* that remapped to the same logical register index.
*/
int getDestIdxNum(PhysRegIndex dest_idx)
{
for (int i=0; i < staticInst->numDestRegs(); i++) {
- if (_destRegIdx[i] == dest_idx)
+ if (_flatDestRegIdx[i] == dest_idx)
return i;
}
* source register to a value. */
void setIntSrc(int idx, uint64_t val);
void setFloatSrc(int idx, FloatReg val);
- void setFloatRegBitsSrc(int idx, uint64_t val);
+ void setFloatRegBitsSrc(int idx, TheISA::FloatRegBits val);
- uint64_t* getIntSrcPtr(int idx) { return &instSrc[idx].integer; }
- uint64_t readIntSrc(int idx) { return instSrc[idx].integer; }
+ TheISA::IntReg* getIntSrcPtr(int idx) { return &instSrc[idx].intVal; }
+ uint64_t readIntSrc(int idx) { return instSrc[idx].intVal; }
/** These Instructions read a integer/float/misc. source register
* value in the instruction. The instruction's execute function will
return instResult[idx].type;
}
- uint64_t readIntResult(int idx)
+ IntReg readIntResult(int idx)
{
- return instResult[idx].val.integer;
+ return instResult[idx].res.intVal;
}
- /** Depending on type, return Float or Double */
- double readFloatResult(int idx)
+ FloatReg readFloatResult(int idx)
{
- return instResult[idx].val.dbl;
+ return instResult[idx].res.fpVal.f;
+ }
+
+ FloatRegBits readFloatBitsResult(int idx)
+ {
+ return instResult[idx].res.fpVal.i;
}
Tick readResultTime(int idx) { return instResult[idx].tick; }
- uint64_t* getIntResultPtr(int idx) { return &instResult[idx].val.integer; }
+ IntReg* getIntResultPtr(int idx) { return &instResult[idx].res.intVal; }
/** This is the interface that an instruction will use to write
* it's destination register.
virtual void setRegOtherThread(unsigned idx, const uint64_t &val,
ThreadID tid = InvalidThreadID);
+ /** Returns the number of consecutive store conditional failures. */
+ unsigned readStCondFailures()
+ { return thread->storeCondFailures; }
+
/** Sets the number of consecutive store conditional failures. */
void setStCondFailures(unsigned sc_failures)
{ thread->storeCondFailures = sc_failures; }
/** Sets this instruction as entered on the CPU Reg Dep Map */
void setRegDepEntry() { status.set(RegDepMapEntry); }
+ /** Unsets this instruction as entered on the CPU Reg Dep Map */
+ void clearRegDepEntry() { status.reset(RegDepMapEntry); }
+
/** Returns whether or not the entry is on the CPU Reg Dep Map */
bool isRegDepEntry() const { return status[RegDepMapEntry]; }
*/
bool eaCalcDone;
- public:
- /** Whether or not the memory operation is done. */
- bool memOpDone;
-
public:
/** Load queue index. */
int16_t lqIdx;
/** Iterator pointing to this BaseDynInst in the list of all insts. */
ListIt instListIt;
+ bool onInstList;
+
/** Returns iterator to this instruction in the list of all insts. */
- ListIt &getInstListIt() { return instListIt; }
+ ListIt getInstListIt() { return instListIt; }
/** Sets iterator for this instruction in the list of all insts. */
- void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
+ void setInstListIt(ListIt _instListIt) { onInstList = true; instListIt = _instListIt; }
/** Count of total number of dynamic instructions. */
static int instcount;
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