cpu: Implement a flat register interface in thread contexts

[gem5.git] / src / cpu / inorder / pipeline_traits.hh

diff --git a/src/cpu/inorder/pipeline_traits.hh b/src/cpu/inorder/pipeline_traits.hh
index 75f01adb1e53fe1e69cb930c030c8d09452f621a..5df61368f797d0c9131fc0b73c65b71b99519ce2 100644 (file)
--- a/src/cpu/inorder/pipeline_traits.hh
+++ b/src/cpu/inorder/pipeline_traits.hh
@@ -38,7 +38,6 @@
 
 #include "arch/isa_traits.hh"
 #include "cpu/base.hh"
-
 #include "params/InOrderCPU.hh"
 
 class InOrderDynInst;
@@ -51,7 +50,7 @@ class ResourceSked;
 namespace ThePipeline {
     // Pipeline Constants
     const unsigned NumStages = 5;
-    const ThreadID MaxThreads = 8;
+    const ThreadID MaxThreads = 1;
     const unsigned BackEndStartStage = 2;
 
     // List of Resources The Pipeline Uses
@@ -78,7 +77,7 @@ namespace ThePipeline {
     //////////////////////////
     typedef ResourceSked ResSchedule;
     typedef ResourceSked* RSkedPtr;
-};
+}