#ifndef __CPU_INORDER_RESOURCE_HH__
#define __CPU_INORDER_RESOURCE_HH__
-#include <vector>
#include <list>
#include <string>
+#include <vector>
#include "base/types.hh"
-#include "cpu/inst_seq.hh"
#include "cpu/inorder/inorder_dyn_inst.hh"
#include "cpu/inorder/pipeline_traits.hh"
+#include "cpu/inst_seq.hh"
#include "sim/eventq.hh"
#include "sim/sim_object.hh"
typedef ResourceRequest ResReq;
typedef ResourceRequest* ResReqPtr;
+class CacheRequest;
+typedef CacheRequest* CacheReqPtr;
+
class Resource {
public:
typedef ThePipeline::DynInstPtr DynInstPtr;
/** Return name of this resource */
virtual std::string name();
- /** Define this function if resource, has a port to connect to an outside
- * simulation object.
- */
- virtual Port* getPort(const std::string &if_name, int idx)
- { return NULL; }
-
/** Return ID for this resource */
int getId() { return id; }
*/
virtual void instGraduated(InstSeqNum seq_num, ThreadID tid) { }
+ /** Post-processsing for Trap Generated from this instruction */
+ virtual void trap(Fault fault, ThreadID tid, DynInstPtr inst) { }
+
/** Request usage of this resource. Returns a ResourceRequest object
* with all the necessary resource information
*/
* if instruction is actually in resource before
* trying to do access.Needs to be defined for derived units.
*/
- virtual Fault doCacheAccess(DynInstPtr inst, uint64_t *res=NULL)
- { panic("doCacheAccess undefined for %s", name()); return NoFault; }
+ virtual void doCacheAccess(DynInstPtr inst, uint64_t *write_result = NULL,
+ CacheReqPtr split_req = NULL)
+ { panic("doCacheAccess undefined for %s", name()); }
+
+ /** Setup Squash to be sent out to pipeline and resource pool */
+ void setupSquash(DynInstPtr inst, int stage_num, ThreadID tid);
/** Squash All Requests After This Seq Num */
virtual void squash(DynInstPtr inst, int stage_num,
InstSeqNum squash_seq_num, ThreadID tid);
+ /** Squash Requests Due to a Memory Stall (By Default, same as "squash" */
virtual void squashDueToMemStall(DynInstPtr inst, int stage_num,
InstSeqNum squash_seq_num, ThreadID tid);
+ /** Handle Squash & Trap that occured from an instruction in a resource */
+ void squashThenTrap(int stage_num, DynInstPtr inst);
+
/** The number of instructions available that this resource can
* can still process
*/
class ResourceEvent : public Event
{
public:
- /** Pointer to the CPU. */
+ /** Pointer to the Resource this is an event for */
Resource *resource;
/// (for InOrderCPU model).
/// check src/sim/eventq.hh for more event priorities.
enum InOrderPriority {
- Resource_Event_Pri = 45,
+ Resource_Event_Pri = 45
};
/** The Resource Slot that this event is servicing */
virtual void process();
/** Returns the description of the resource event. */
- const char *description();
+ const char *description() const;
/** Set slot idx for event */
void setSlot(int slot) { slotIdx = slot; }
ResourceRequest(Resource *_res);
virtual ~ResourceRequest();
+
+ std::string name();
int reqID;
- virtual void setRequest(DynInstPtr _inst, int stage_num,
+ void setRequest(DynInstPtr _inst, int stage_num,
int res_idx, int slot_num, unsigned _cmd);
virtual void clearRequest();
*/
void done(bool completed = true);
+ void freeSlot();
+
/////////////////////////////////////////////
//
// GET RESOURCE REQUEST IDENTIFICATION / INFO
/** Get Slot Number */
int getSlot() { return slotNum; }
- int getComplSlot() { return complSlotNum; }
bool hasSlot() { return slotNum >= 0; }
/** Get Stage Number */
bool valid;
+ bool doneInResource;
+
////////////////////////////////////////
//
// GET RESOURCE REQUEST STATUS FROM VARIABLES
/** Get/Set IsProcessing variables */
bool isProcessing() { return processing; }
- void setProcessing() { processing = true; }
+ void setProcessing(bool cond = true) { processing = cond; }
/** Get/Set IsWaiting variables */
bool isMemStall() { return memStall; }
int stageNum;
int resIdx;
int slotNum;
- int complSlotNum;
/** Resource Request Status */
bool completed;