MEM: Enable multiple distributed generalized memories

[gem5.git] / src / cpu / inorder / resource.hh

diff --git a/src/cpu/inorder/resource.hh b/src/cpu/inorder/resource.hh
index fcf01065a8ba849dc030036dafadfc4e977837a5..3c1a8cc470e802d2995af82e18e4c559a268056b 100644 (file)
--- a/src/cpu/inorder/resource.hh
+++ b/src/cpu/inorder/resource.hh
@@ -51,6 +51,9 @@ class ResourceRequest;
 typedef ResourceRequest ResReq;
 typedef ResourceRequest* ResReqPtr;
 
+class CacheRequest;
+typedef CacheRequest* CacheReqPtr;
+
 class Resource {
   public:
     typedef ThePipeline::DynInstPtr DynInstPtr;
@@ -67,12 +70,6 @@ class Resource {
     /** Return name of this resource */
     virtual std::string name();
 
-    /** Define this function if resource, has a port to connect to an outside
-     *  simulation object.
-     */
-    virtual Port* getPort(const std::string &if_name, int idx) 
-    { return NULL; }
-
     /** Return ID for this resource */
     int getId() { return id; }
 
@@ -154,8 +151,9 @@ class Resource {
      *  if instruction is actually in resource before
      *  trying to do access.Needs to be defined for derived units.
      */
-    virtual Fault doCacheAccess(DynInstPtr inst, uint64_t *res=NULL)
-    { panic("doCacheAccess undefined for %s", name()); return NoFault; }
+    virtual void doCacheAccess(DynInstPtr inst, uint64_t *write_result = NULL,
+                               CacheReqPtr split_req = NULL)
+    { panic("doCacheAccess undefined for %s", name()); }
 
     /** Setup Squash to be sent out to pipeline and resource pool */
     void setupSquash(DynInstPtr inst, int stage_num, ThreadID tid);
@@ -168,6 +166,9 @@ class Resource {
     virtual void squashDueToMemStall(DynInstPtr inst, int stage_num,
                                      InstSeqNum squash_seq_num, ThreadID tid);
 
+    /** Handle Squash & Trap that occured from an instruction in a resource */
+    void squashThenTrap(int stage_num, DynInstPtr inst);
+
     /** The number of instructions available that this resource can
      *  can still process
      */
@@ -262,7 +263,7 @@ class ResourceEvent : public Event
     /// (for InOrderCPU model).
     /// check src/sim/eventq.hh for more event priorities.
     enum InOrderPriority {
-        Resource_Event_Pri = 45,
+        Resource_Event_Pri = 45
     };
 
     /** The Resource Slot that this event is servicing */
@@ -280,7 +281,7 @@ class ResourceEvent : public Event
     virtual void process();
 
     /** Returns the description of the resource event. */
-    const char *description();
+    const char *description() const;
 
     /** Set slot idx for event */
     void setSlot(int slot) { slotIdx = slot; }
@@ -317,7 +318,7 @@ class ResourceRequest
     
     int reqID;
 
-    virtual void setRequest(DynInstPtr _inst, int stage_num,
+    void setRequest(DynInstPtr _inst, int stage_num,
                     int res_idx, int slot_num, unsigned _cmd);
 
     virtual void clearRequest();
@@ -389,7 +390,7 @@ class ResourceRequest
 
     /** Get/Set IsProcessing variables */
     bool isProcessing() { return processing; }
-    void setProcessing() { processing = true; }
+    void setProcessing(bool cond = true) { processing = cond; }
 
     /** Get/Set IsWaiting variables */
     bool isMemStall() { return memStall; }