/*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2007 MIPS Technologies, Inc.
* All rights reserved.
*
#ifndef __CPU_INORDER_RESOURCE_POOL_HH__
#define __CPU_INORDER_RESOURCE_POOL_HH__
-#include <vector>
-#include <list>
#include <string>
+#include <vector>
-#include "cpu/inst_seq.hh"
+#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/inorder_dyn_inst.hh"
-#include "cpu/inorder/resource.hh"
-#include "cpu/inorder/pipeline_traits.hh"
#include "cpu/inorder/params.hh"
+#include "cpu/inorder/pipeline_traits.hh"
+#include "cpu/inorder/resource.hh"
+#include "cpu/inst_seq.hh"
#include "params/InOrderCPU.hh"
-#include "cpu/inorder/cpu.hh"
#include "sim/eventq.hh"
#include "sim/sim_object.hh"
+class CacheUnit;
class Event;
-class InOrderCPU;
-class Resource;
+class FetchUnit;
class ResourceEvent;
class ResourcePool {
Default
};
+ enum ResPoolEventPri {
+ ResPool_Pri = InOrderCPU::InOrderCPU_Pri - 5,
+ ResGrad_Pri,
+ ResSquash_Pri
+ };
+
class ResPoolEvent : public Event
{
protected:
DynInstPtr _inst,
int stage_num,
InstSeqNum seq_num,
- ThreadID _tid);
+ ThreadID _tid,
+ ResPoolEventPri res_pri = ResPool_Pri);
/** Set Type of Event To Be Scheduled */
void setEvent(InOrderCPU::CPUEventType e_type,
}
/** Processes a resource event. */
- virtual void process();
+ void process();
/** Returns the description of the resource event. */
- const char *description();
+ const char *description() const;
/** Schedule Event */
- void scheduleEvent(int delay);
+ void scheduleEvent(Cycles delay);
/** Unschedule This Event */
void unscheduleEvent();
public:
ResourcePool(InOrderCPU *_cpu, ThePipeline::Params *params);
- ~ResourcePool();
+ virtual ~ResourcePool();
std::string name();
void init();
+ void print();
+
/** Register Statistics in All Resources */
void regStats();
- /** Returns a specific port. */
- Port* getPort(const std::string &if_name, int idx);
-
- /** Returns a specific port. */
- unsigned getPortIdx(const std::string &port_name);
-
/** Returns a specific resource. */
- unsigned getResIdx(const std::string &res_name);
+ unsigned getResIdx(const ThePipeline::ResourceId &res_id);
/** Returns a pointer to a resource */
Resource* getResource(int res_idx) { return resources[res_idx]; }
InstSeqNum done_seq_num, ThreadID tid);
/** Activate Thread in all resources */
- void activateAll(ThreadID tid);
+ void activateThread(ThreadID tid);
/** De-Activate Thread in all resources */
- void deactivateAll(ThreadID tid);
+ void deactivateThread(ThreadID tid);
- /** De-Activate Thread in all resources */
- void suspendAll(ThreadID tid);
+ /** Suspend Thread in all resources */
+ void suspendThread(ThreadID tid);
/** Broadcast Context Switch Update to all resources */
void updateAfterContextSwitch(DynInstPtr inst, ThreadID tid);
/** Broadcast graduation to all resources */
void instGraduated(InstSeqNum seq_num, ThreadID tid);
+ /** Broadcast trap to all resources */
+ void trap(Fault fault, ThreadID tid, DynInstPtr inst);
+
/** The number of instructions available that a resource can
* can still process.
*/
/** Schedule resource event, regardless of its current state. */
void scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst = NULL,
- int delay = 0, int res_idx = 0, ThreadID tid = 0);
+ Cycles delay = Cycles(0), int res_idx = 0,
+ ThreadID tid = 0);
/** UnSchedule resource event, regardless of its current state. */
void unscheduleEvent(int res_idx, DynInstPtr inst);
DynInstPtr dummyInst[ThePipeline::MaxThreads];
+ /**
+ * Get a pointer to the (always present) instruction fetch unit.
+ *
+ * @return the instruction unit
+ */
+ FetchUnit *getInstUnit() const { return instUnit; }
+
+ /**
+ * Get a pointer to the (always present) data load/store unit.
+ *
+ * @return the data cache unit
+ */
+ CacheUnit *getDataUnit() const { return dataUnit; }
+
private:
- std::vector<Resource *> resources;
- std::vector<int> memObjects;
+ /** The instruction fetch unit. */
+ FetchUnit *instUnit;
+
+ /** The data load/store unit. */
+ CacheUnit *dataUnit;
+
+ std::vector<Resource *> resources;
+ /** Resources that need to be updated on an inst. graduation */
+ std::vector<int> gradObjects;
};
#endif //__CPU_INORDER_RESOURCE_HH__