Yet another merge with the main repository.

[gem5.git] / src / cpu / inorder / resources / cache_unit.hh

diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh
index 097b6fa7abd978b4153a758b40105d9435ec0456..2155c920c7fe314690e5f9f63b4bec607f610fec 100644 (file)
--- a/src/cpu/inorder/resources/cache_unit.hh
+++ b/src/cpu/inorder/resources/cache_unit.hh
@@ -32,12 +32,13 @@
 #ifndef __CPU_INORDER_CACHE_UNIT_HH__
 #define __CPU_INORDER_CACHE_UNIT_HH__
 
-#include <vector>
 #include <list>
 #include <string>
+#include <vector>
 
 #include "arch/predecoder.hh"
 #include "arch/tlb.hh"
+#include "base/hashmap.hh"
 #include "config/the_isa.hh"
 #include "cpu/inorder/inorder_dyn_inst.hh"
 #include "cpu/inorder/pipeline_traits.hh"
@@ -92,25 +93,17 @@ class CacheUnit : public Resource
             cachePortUnit(_cachePortUnit)
         { }
 
-        bool snoopRangeSent;
-
       protected:
         /** Atomic version of receive.  Panics. */
         Tick recvAtomic(PacketPtr pkt);
 
-        /** Functional version of receive.  Panics. */
+        /** Functional version of receive.*/
         void recvFunctional(PacketPtr pkt);
 
-        /** Receives status change.  Other than range changing, panics. */
-        void recvStatusChange(Status status);
-
-        /** Returns the address ranges of this device. */
-        void getDeviceAddressRanges(AddrRangeList &resp,
-                                            AddrRangeList &snoop)
-        { resp.clear(); snoop.clear(); }
+        /** Receives range changes. */
+        void recvRangeChange();
 
-        /** Timing version of receive. Handles setting fetch to the
-         * proper status to start fetching. */
+        /** Timing version of receive */
         bool recvTiming(PacketPtr pkt);
 
         /** Handles doing a retry of a failed fetch. */
@@ -150,6 +143,14 @@ class CacheUnit : public Resource
     virtual void setupMemRequest(DynInstPtr inst, CacheReqPtr cache_req,
                                  int acc_size, int flags);
 
+    void finishCacheUnitReq(DynInstPtr inst, CacheRequest *cache_req);
+
+    void buildDataPacket(CacheRequest *cache_req);
+
+    bool processSquash(CacheReqPacket *cache_pkt);
+
+    void trap(Fault fault, ThreadID tid, DynInstPtr inst);
+
     void recvRetry();
 
     /** Returns a specific port. */
@@ -181,9 +182,9 @@ class CacheUnit : public Resource
 
     bool cachePortBlocked;
 
-    std::vector<Addr> addrList[ThePipeline::MaxThreads];
+    std::list<Addr> addrList[ThePipeline::MaxThreads];
 
-    std::map<Addr, InstSeqNum> addrMap[ThePipeline::MaxThreads];
+    m5::hash_map<Addr, InstSeqNum> addrMap[ThePipeline::MaxThreads];
 
   public:
     int cacheBlkSize;
@@ -197,9 +198,9 @@ class CacheUnit : public Resource
     }
 
     bool tlbBlocked[ThePipeline::MaxThreads];
+    InstSeqNum tlbBlockSeqNum[ThePipeline::MaxThreads];
 
     TheISA::TLB* tlb();
-
     TheISA::TLB *_tlb;
 };
 
@@ -225,7 +226,7 @@ class CacheRequest : public ResourceRequest
   public:
     CacheRequest(CacheUnit *cres)
         :  ResourceRequest(cres), memReq(NULL), reqData(NULL),
-           dataPkt(NULL), retryPkt(NULL), memAccComplete(false),
+           dataPkt(NULL), memAccComplete(false),
            memAccPending(false), tlbStall(false), splitAccess(false),
            splitAccessNum(-1), split2ndAccess(false),
            fetchBufferFill(false)
@@ -233,9 +234,8 @@ class CacheRequest : public ResourceRequest
 
     virtual ~CacheRequest()
     {
-        if (reqData && !splitAccess) {
+        if (reqData && !splitAccess)
             delete [] reqData;
-        }
     }
 
     void setRequest(DynInstPtr _inst, int stage_num, int res_idx, int slot_num,
@@ -247,27 +247,7 @@ class CacheRequest : public ResourceRequest
         ResourceRequest::setRequest(_inst, stage_num, res_idx, slot_num, _cmd);
     }
 
-    void clearRequest()
-    {
-        if (reqData && !splitAccess) {
-            delete [] reqData;
-        }
-
-        memReq = NULL;
-        reqData = NULL;
-        dataPkt = NULL;
-        retryPkt = NULL;
-        memAccComplete = false;
-        memAccPending = false;
-        tlbStall = false;
-        splitAccess = false;
-        splitAccessNum = -1;
-        split2ndAccess = false;
-        instIdx = 0;
-        fetchBufferFill = false;
-
-        ResourceRequest::clearRequest();
-    }
+    void clearRequest();
 
     virtual PacketDataPtr getData()
     { return reqData; }
@@ -292,8 +272,7 @@ class CacheRequest : public ResourceRequest
     MemCmd::Command pktCmd;
     RequestPtr memReq;
     PacketDataPtr reqData;
-    PacketPtr dataPkt;
-    PacketPtr retryPkt;
+    CacheReqPacket *dataPkt;
 
     bool memAccComplete;
     bool memAccPending;
@@ -313,14 +292,17 @@ class CacheReqPacket : public Packet
   public:
     CacheReqPacket(CacheRequest *_req,
                    Command _cmd, short _dest, int _idx = 0)
-        : Packet(_req->memReq, _cmd, _dest), cacheReq(_req), instIdx(_idx)
+        : Packet(&(*_req->memReq), _cmd, _dest), cacheReq(_req),
+          instIdx(_idx), hasSlot(false), reqData(NULL), memReq(NULL)
     {
 
     }
 
     CacheRequest *cacheReq;
     int instIdx;
-    
+    bool hasSlot;
+    PacketDataPtr reqData;
+    RequestPtr memReq;
 };
 
 #endif //__CPU_CACHE_UNIT_HH__