Yet another merge with the main repository.

[gem5.git] / src / cpu / inorder / resources / cache_unit.hh

diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh
index dd6fa763878173a4b757d593675ca8bc9e95ada6..2155c920c7fe314690e5f9f63b4bec607f610fec 100644 (file)
--- a/src/cpu/inorder/resources/cache_unit.hh
+++ b/src/cpu/inorder/resources/cache_unit.hh
@@ -38,6 +38,7 @@
 
 #include "arch/predecoder.hh"
 #include "arch/tlb.hh"
+#include "base/hashmap.hh"
 #include "config/the_isa.hh"
 #include "cpu/inorder/inorder_dyn_inst.hh"
 #include "cpu/inorder/pipeline_traits.hh"
@@ -92,25 +93,17 @@ class CacheUnit : public Resource
             cachePortUnit(_cachePortUnit)
         { }
 
-        bool snoopRangeSent;
-
       protected:
         /** Atomic version of receive.  Panics. */
         Tick recvAtomic(PacketPtr pkt);
 
-        /** Functional version of receive.  Panics. */
+        /** Functional version of receive.*/
         void recvFunctional(PacketPtr pkt);
 
-        /** Receives status change.  Other than range changing, panics. */
-        void recvStatusChange(Status status);
-
-        /** Returns the address ranges of this device. */
-        void getDeviceAddressRanges(AddrRangeList &resp,
-                                            AddrRangeList &snoop)
-        { resp.clear(); snoop.clear(); }
+        /** Receives range changes. */
+        void recvRangeChange();
 
-        /** Timing version of receive. Handles setting fetch to the
-         * proper status to start fetching. */
+        /** Timing version of receive */
         bool recvTiming(PacketPtr pkt);
 
         /** Handles doing a retry of a failed fetch. */
@@ -156,6 +149,8 @@ class CacheUnit : public Resource
 
     bool processSquash(CacheReqPacket *cache_pkt);
 
+    void trap(Fault fault, ThreadID tid, DynInstPtr inst);
+
     void recvRetry();
 
     /** Returns a specific port. */
@@ -203,9 +198,9 @@ class CacheUnit : public Resource
     }
 
     bool tlbBlocked[ThePipeline::MaxThreads];
+    InstSeqNum tlbBlockSeqNum[ThePipeline::MaxThreads];
 
     TheISA::TLB* tlb();
-
     TheISA::TLB *_tlb;
 };