MEM: Introduce the master/slave port sub-classes in C++

[gem5.git] / src / cpu / inorder / resources / cache_unit.hh

diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh
index d9f98e42cc3af21d8db7f59c0de9bb798a8e7353..3f3ef12e62210ed97e72cd023ad8b4518f777e98 100644 (file)
--- a/src/cpu/inorder/resources/cache_unit.hh
+++ b/src/cpu/inorder/resources/cache_unit.hh
@@ -139,7 +139,7 @@ class CacheUnit : public Resource
     
   protected:
     /** Cache interface. */
-    Port *cachePort;
+    MasterPort *cachePort;
 
     bool cachePortBlocked;