#include "config/the_isa.hh"
#include "cpu/inorder/resources/fetch_seq_unit.hh"
#include "cpu/inorder/resource_pool.hh"
+#include "debug/InOrderFetchSeq.hh"
+#include "debug/InOrderStall.hh"
using namespace std;
using namespace TheISA;
using namespace ThePipeline;
FetchSeqUnit::FetchSeqUnit(std::string res_name, int res_id, int res_width,
- int res_latency, InOrderCPU *_cpu,
+ Cycles res_latency, InOrderCPU *_cpu,
ThePipeline::Params *params)
: Resource(res_name, res_id, res_width, res_latency, _cpu),
instSize(sizeof(MachInst))
pcValid[tid] = false;
pcBlockStage[tid] = 0;
+ //@todo: Use CPU's squashSeqNum here instead of maintaining our own
+ // state
squashSeqNum[tid] = (InstSeqNum)-1;
lastSquashCycle[tid] = 0;
}
{
resourceEvent = new FetchSeqEvent[width];
+ for (int i = 0; i < width; i++) {
+ reqs[i] = new ResourceRequest(this);
+ }
+
initSlots();
}
void
FetchSeqUnit::execute(int slot_num)
{
- ResourceRequest* fs_req = reqMap[slot_num];
+ ResourceRequest* fs_req = reqs[slot_num];
DynInstPtr inst = fs_req->inst;
ThreadID tid = inst->readTid();
int stage_num = fs_req->getStageNum();
- int seq_num = inst->seqNum;
- DPRINTF(InOrderFetchSeq, "[tid:%i]: Current PC is %s\n", tid,
- pc[tid]);
+ if (inst->fault != NoFault) {
+ DPRINTF(InOrderFetchSeq,
+ "[tid:%i]: [sn:%i]: Detected %s fault @ %x. Forwarding to "
+ "next stage.\n", tid, inst->seqNum, inst->fault->name(),
+ inst->pcState());
+ fs_req->done();
+ return;
+ }
switch (fs_req->cmd)
{
case AssignNextPC:
{
+ DPRINTF(InOrderFetchSeq, "[tid:%i]: Current PC is %s\n", tid,
+ pc[tid]);
+
if (pcValid[tid]) {
inst->pcState(pc[tid]);
inst->setMemAddr(pc[tid].instAddr());
fs_req->done();
} else {
DPRINTF(InOrderStall, "STALL: [tid:%i]: NPC not valid\n", tid);
- fs_req->setCompleted(false);
+ fs_req->done(false);
}
}
break;
case UpdateTargetPC:
{
+ assert(!inst->isCondDelaySlot() &&
+ "Not Handling Conditional Delay Slot");
+
if (inst->isControl()) {
- // If it's a return, then we must wait for resolved address.
if (inst->isReturn() && !inst->predTaken()) {
+ // If it's a return, then we must wait for resolved address.
+ // The Predictor will mark a return a false as "not taken"
+ // if there is no RAS entry
+ DPRINTF(InOrderFetchSeq, "[tid:%d]: Setting block signal "
+ "for stage %i.\n",
+ tid, stage_num);
cpu->pipelineStage[stage_num]->
toPrevStages->stageBlock[stage_num][tid] = true;
pcValid[tid] = false;
pcBlockStage[tid] = stage_num;
- } else if (inst->isCondDelaySlot() && !inst->predTaken()) {
- // Not-Taken AND Conditional Control
- DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: [PC:%s] "
- "Predicted Not-Taken Cond. Delay inst. Skipping "
- "delay slot and Updating PC to %s\n",
- tid, inst->seqNum, inst->pcState(),
- inst->readPredTarg());
-
- DPRINTF(InOrderFetchSeq, "[tid:%i] Setting up squash to "
- "start from stage %i, after [sn:%i].\n", tid,
- stage_num, seq_num);
-
- inst->bdelaySeqNum = seq_num;
- inst->squashingStage = stage_num;
-
- squashAfterInst(inst, stage_num, tid);
- } else if (!inst->isCondDelaySlot() && !inst->predTaken()) {
- // Not-Taken Control
- DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: Predicted "
- "Not-Taken Control "
- "inst. updating PC to %s\n", tid, inst->seqNum,
- inst->readPredTarg());
-#if ISA_HAS_DELAY_SLOT
- pc[tid] = inst->pcState();
- advancePC(pc[tid], inst->staticInst);
-#endif
} else if (inst->predTaken()) {
// Taken Control
-#if ISA_HAS_DELAY_SLOT
- pc[tid] = inst->readPredTarg();
-
- DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i] Updating delay"
- " slot target to PC %s\n", tid, inst->seqNum,
- inst->readPredTarg());
- inst->bdelaySeqNum = seq_num + 1;
-#else
- inst->bdelaySeqNum = seq_num;
-#endif
-
- inst->squashingStage = stage_num;
+ inst->setSquashInfo(stage_num);
+ setupSquash(inst, stage_num, tid);
+
DPRINTF(InOrderFetchSeq, "[tid:%i] Setting up squash to "
"start from stage %i, after [sn:%i].\n",
- tid, stage_num, inst->bdelaySeqNum);
-
- // Do Squashing
- squashAfterInst(inst, stage_num, tid);
+ tid, stage_num, inst->squashSeqNum);
}
} else {
DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: Ignoring branch "
}
}
-inline void
-FetchSeqUnit::squashAfterInst(DynInstPtr inst, int stage_num, ThreadID tid)
-{
- // Squash In Pipeline Stage
- cpu->pipelineStage[stage_num]->squashDueToBranch(inst, tid);
-
- // Squash inside current resource, so if there needs to be fetching on
- // same cycle the fetch information will be correct.
-
- // Schedule Squash Through-out Resource Pool
- cpu->resPool->scheduleEvent(
- (InOrderCPU::CPUEventType)ResourcePool::SquashAll, inst, 0);
-}
-
void
FetchSeqUnit::squash(DynInstPtr inst, int squash_stage,
InstSeqNum squash_seq_num, ThreadID tid)
{
- DPRINTF(InOrderFetchSeq, "[tid:%i]: Updating due to squash from stage %i."
- "\n", tid, squash_stage);
-
- InstSeqNum done_seq_num = inst->bdelaySeqNum;
-
- // Handles the case where we are squashing because of something that is
- // not a branch...like a memory stall
- TheISA::PCState newPC;
- if (inst->isControl()) {
- newPC = inst->readPredTarg();
- } else {
- TheISA::PCState thisPC = inst->pcState();
- assert(inst->staticInst);
- advancePC(thisPC, inst->staticInst);
- newPC = thisPC;
- }
+ DPRINTF(InOrderFetchSeq, "[tid:%i]: Updating due to squash from %s (%s) "
+ "stage %i.\n", tid, inst->instName(), inst->pcState(),
+ squash_stage);
- if (squashSeqNum[tid] <= done_seq_num &&
- lastSquashCycle[tid] == curTick()) {
+ if (lastSquashCycle[tid] == curTick() &&
+ squashSeqNum[tid] <= squash_seq_num) {
DPRINTF(InOrderFetchSeq, "[tid:%i]: Ignoring squash from stage %i, "
"since there is an outstanding squash that is older.\n",
tid, squash_stage);
} else {
- squashSeqNum[tid] = done_seq_num;
+ squashSeqNum[tid] = squash_seq_num;
lastSquashCycle[tid] = curTick();
- // If The very next instruction number is the done seq. num,
- // then we haven't seen the delay slot yet ... if it isn't
- // the last done_seq_num then this is the delay slot inst.
- if (cpu->nextInstSeqNum(tid) != done_seq_num &&
- !inst->procDelaySlotOnMispred) {
-
- // Reset PC
- pc[tid] = newPC;
-#if ISA_HAS_DELAY_SLOT
- TheISA::advancePC(pc[tid], inst->staticInst);
-#endif
-
- DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC to %s.\n",
- tid, newPC);
- } else {
- assert(ISA_HAS_DELAY_SLOT);
-
- pc[tid] = (inst->procDelaySlotOnMispred) ?
- inst->branchTarget() : newPC;
-
- // Reset PC to Delay Slot Instruction
- if (inst->procDelaySlotOnMispred) {
- // Reset PC
- pc[tid] = newPC;
- }
+ if (inst->staticInst) {
+ if (inst->fault != NoFault) {
+ // A Trap Caused This Fault and will update the pc state
+ // when done trapping
+ DPRINTF(InOrderFetchSeq, "[tid:%i] Blocking due to fault @ "
+ "[sn:%i].%s %s \n", tid, inst->seqNum,
+ inst->instName(), inst->pcState());
+ pcValid[tid] = false;
+ } else {
+ TheISA::PCState nextPC;
+ assert(inst->staticInst);
+ if (inst->isControl()) {
+ nextPC = inst->readPredTarg();
+
+ // If we are already fetching this PC then advance to next PC
+ // =======
+ // This should handle ISAs w/delay slots and annulled delay
+ // slots to figure out which is the next PC to fetch after
+ // a mispredict
+ DynInstPtr bdelay_inst = NULL;
+ ListIt bdelay_it;
+ if (inst->onInstList) {
+ bdelay_it = inst->getInstListIt();
+ bdelay_it++;
+ } else {
+ InstSeqNum branch_delay_num = inst->seqNum + 1;
+ bdelay_it = cpu->findInst(branch_delay_num, tid);
+ }
+
+ if (bdelay_it != cpu->instList[tid].end()) {
+ bdelay_inst = (*bdelay_it);
+ }
+
+ if (bdelay_inst) {
+ if (bdelay_inst->pc.instAddr() == nextPC.instAddr()) {
+ bdelay_inst->pc = nextPC;
+ advancePC(nextPC, inst->staticInst);
+ DPRINTF(InOrderFetchSeq, "Advanced PC to %s\n", nextPC);
+ }
+ }
+ } else {
+ nextPC = inst->pcState();
+ advancePC(nextPC, inst->staticInst);
+ }
- }
- // Unblock Any Stages Waiting for this information to be updated ...
- if (!pcValid[tid]) {
- cpu->pipelineStage[pcBlockStage[tid]]->
- toPrevStages->stageUnblock[pcBlockStage[tid]][tid] = true;
- }
+ DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC to %s.\n",
+ tid, nextPC);
+ pc[tid] = nextPC;
+
+ // Unblock Any Stages Waiting for this information to be updated ...
+ if (!pcValid[tid]) {
+ DPRINTF(InOrderFetchSeq, "[tid:%d]: Setting unblock signal "
+ "for stage %i.\n",
+ tid, pcBlockStage[tid]);
+
+ // Need to use "fromNextStages" instead of "toPrevStages"
+ // because the timebuffer will have already have advanced
+ // in the tick function and this squash function will happen after
+ // the tick
+ cpu->pipelineStage[pcBlockStage[tid]]->
+ fromNextStages->stageUnblock[pcBlockStage[tid]][tid] = true;
+ }
- pcValid[tid] = true;
+ pcValid[tid] = true;
+ }
+ }
}
Resource::squash(inst, squash_stage, squash_seq_num, tid);
deactivateThread(tid);
}
+void
+FetchSeqUnit::trap(const Fault &fault, ThreadID tid, DynInstPtr inst)
+{
+ pcValid[tid] = true;
+ pc[tid] = cpu->pcState(tid);
+ DPRINTF(InOrderFetchSeq, "[tid:%i]: Trap updating to PC: "
+ "%s.\n", tid, pc[tid]);
+}
+
void
FetchSeqUnit::updateAfterContextSwitch(DynInstPtr inst, ThreadID tid)
{
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