#ifndef __CPU_INORDER_FETCH_SEQ_UNIT_HH__
#define __CPU_INORDER_FETCH_SEQ_UNIT_HH__
-#include <vector>
#include <list>
#include <string>
+#include <vector>
#include "config/the_isa.hh"
-#include "cpu/inorder/resource.hh"
+#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/inorder_dyn_inst.hh"
#include "cpu/inorder/pipeline_traits.hh"
-#include "cpu/inorder/cpu.hh"
+#include "cpu/inorder/resource.hh"
class FetchSeqUnit : public Resource {
public:
typedef ThePipeline::DynInstPtr DynInstPtr;
+ typedef std::list<DynInstPtr>::iterator ListIt;
enum Command {
AssignNextPC,
public:
FetchSeqUnit(std::string res_name, int res_id, int res_width,
int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
- virtual ~FetchSeqUnit();
+ ~FetchSeqUnit();
- virtual void init();
- virtual void activateThread(ThreadID tid);
- virtual void deactivateThread(ThreadID tid);
- virtual void suspendThread(ThreadID tid);
- virtual void execute(int slot_num);
+ void init();
+ void activateThread(ThreadID tid);
+ void deactivateThread(ThreadID tid);
+ void suspendThread(ThreadID tid);
+ void execute(int slot_num);
void updateAfterContextSwitch(DynInstPtr inst, ThreadID tid);
- /** Override default Resource squash sequence. This actually,
- * looks in the global communication buffer to get squash
- * info
- */
- virtual void squash(DynInstPtr inst, int squash_stage,
- InstSeqNum squash_seq_num, ThreadID tid);
-
+ /** Update to correct PC from a squash */
+ void squash(DynInstPtr inst, int squash_stage,
+ InstSeqNum squash_seq_num, ThreadID tid);
- inline void squashAfterInst(DynInstPtr inst, int stage_num, ThreadID tid);
+ /** Update to correct PC from a trap */
+ void trap(Fault fault, ThreadID tid, DynInstPtr inst);
protected:
unsigned instSize;
bool pcValid[ThePipeline::MaxThreads];
int pcBlockStage[ThePipeline::MaxThreads];
- TheISA::IntReg PC[ThePipeline::MaxThreads];
- TheISA::IntReg nextPC[ThePipeline::MaxThreads];
- TheISA::IntReg nextNPC[ThePipeline::MaxThreads];
-
- /** Tracks delay slot information for threads in ISAs which use
- * delay slots;
- */
- struct DelaySlotInfo {
- InstSeqNum delaySlotSeqNum;
- InstSeqNum branchSeqNum;
- int numInsts;
- Addr targetAddr;
- bool targetReady;
- };
-
- DelaySlotInfo delaySlotInfo[ThePipeline::MaxThreads];
+ TheISA::PCState pc[ThePipeline::MaxThreads];
/** Squash Seq. Nums*/
InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
public:
/** Constructs a resource event. */
FetchSeqEvent();
- virtual ~FetchSeqEvent() {}
+ ~FetchSeqEvent() {}
/** Processes a resource event. */
- virtual void process();
+ void process();
};
};