Yet another merge with the main repository.

[gem5.git] / src / cpu / inorder / resources / fetch_seq_unit.hh

diff --git a/src/cpu/inorder/resources/fetch_seq_unit.hh b/src/cpu/inorder/resources/fetch_seq_unit.hh
index fdbc4521f989862ed6b0269f01f311fe393f7b55..1cd0047e2e5affbec5bc20788d2b21e783b5ea7b 100644 (file)
--- a/src/cpu/inorder/resources/fetch_seq_unit.hh
+++ b/src/cpu/inorder/resources/fetch_seq_unit.hh
@@ -32,19 +32,20 @@
 #ifndef __CPU_INORDER_FETCH_SEQ_UNIT_HH__
 #define __CPU_INORDER_FETCH_SEQ_UNIT_HH__
 
-#include <vector>
 #include <list>
 #include <string>
+#include <vector>
 
 #include "config/the_isa.hh"
-#include "cpu/inorder/resource.hh"
+#include "cpu/inorder/cpu.hh"
 #include "cpu/inorder/inorder_dyn_inst.hh"
 #include "cpu/inorder/pipeline_traits.hh"
-#include "cpu/inorder/cpu.hh"
+#include "cpu/inorder/resource.hh"
 
 class FetchSeqUnit : public Resource {
   public:
     typedef ThePipeline::DynInstPtr DynInstPtr;
+    typedef std::list<DynInstPtr>::iterator ListIt;
 
     enum Command {
         AssignNextPC,
@@ -54,23 +55,22 @@ class FetchSeqUnit : public Resource {
   public:
     FetchSeqUnit(std::string res_name, int res_id, int res_width,
               int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
-    virtual ~FetchSeqUnit() {}
-
-    virtual void init();
-    virtual void activateThread(ThreadID tid);
-    virtual void deactivateThread(ThreadID tid);
-    virtual void suspendThread(ThreadID tid);
-    virtual void execute(int slot_num);
-
-    /** Override default Resource squash sequence. This actually,
-     *  looks in the global communication buffer to get squash
-     *  info
-     */
-    virtual void squash(DynInstPtr inst, int squash_stage,
-                        InstSeqNum squash_seq_num, ThreadID tid);
-
-
-    inline void squashAfterInst(DynInstPtr inst, int stage_num, ThreadID tid);
+    ~FetchSeqUnit();
+    
+    void init();
+    void activateThread(ThreadID tid);
+    void deactivateThread(ThreadID tid);
+    void suspendThread(ThreadID tid);
+    void execute(int slot_num);
+    void updateAfterContextSwitch(DynInstPtr inst, ThreadID tid);
+    
+
+    /** Update to correct PC from a squash */
+    void squash(DynInstPtr inst, int squash_stage,
+                InstSeqNum squash_seq_num, ThreadID tid);
+
+    /** Update to correct PC from a trap */
+    void trap(Fault fault, ThreadID tid, DynInstPtr inst);
 
   protected:
     unsigned instSize;
@@ -78,22 +78,7 @@ class FetchSeqUnit : public Resource {
     bool pcValid[ThePipeline::MaxThreads];
     int pcBlockStage[ThePipeline::MaxThreads];
 
-    TheISA::IntReg PC[ThePipeline::MaxThreads];
-    TheISA::IntReg nextPC[ThePipeline::MaxThreads];
-    TheISA::IntReg nextNPC[ThePipeline::MaxThreads];
-
-    /** Tracks delay slot information for threads in ISAs which use
-     * delay slots;
-     */
-    struct DelaySlotInfo {
-        InstSeqNum delaySlotSeqNum;
-        InstSeqNum branchSeqNum;
-        int numInsts;
-        Addr targetAddr;
-        bool targetReady;
-    };
-
-    DelaySlotInfo delaySlotInfo[ThePipeline::MaxThreads];
+    TheISA::PCState pc[ThePipeline::MaxThreads];
 
     /** Squash Seq. Nums*/
     InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
@@ -108,10 +93,10 @@ class FetchSeqUnit : public Resource {
       public:
         /** Constructs a resource event. */
         FetchSeqEvent();
-        virtual ~FetchSeqEvent() {}
+        ~FetchSeqEvent() {}
 
         /** Processes a resource event. */
-        virtual void process();
+        void process();
     };
 
 };