cpu: Update DRAM traffic gen

[gem5.git] / src / cpu / inorder / resources / fetch_unit.cc

diff --git a/src/cpu/inorder/resources/fetch_unit.cc b/src/cpu/inorder/resources/fetch_unit.cc
index 07669ef2a9f1cf6332f792b772c9123b9f1b378b..6892688b2828b83391ea405b628741ee4c43a419 100644 (file)
--- a/src/cpu/inorder/resources/fetch_unit.cc
+++ b/src/cpu/inorder/resources/fetch_unit.cc
@@ -53,13 +53,13 @@ using namespace TheISA;
 using namespace ThePipeline;
 
 FetchUnit::FetchUnit(string res_name, int res_id, int res_width,
-                     int res_latency, InOrderCPU *_cpu,
+                     Cycles res_latency, InOrderCPU *_cpu,
                      ThePipeline::Params *params)
     : CacheUnit(res_name, res_id, res_width, res_latency, _cpu, params),
       instSize(sizeof(TheISA::MachInst)), fetchBuffSize(params->fetchBuffSize)
 {
     for (int tid = 0; tid < MaxThreads; tid++)
-        decoder[tid] = new Decoder(NULL);
+        decoder[tid] = new Decoder;
 }
 
 FetchUnit::~FetchUnit()
@@ -109,7 +109,6 @@ FetchUnit::createMachInst(std::list<FetchBlock*>::iterator fetch_it,
     MachInst mach_inst =
         TheISA::gtoh(fetchInsts[fetch_offset]);
 
-    decoder[tid]->setTC(cpu->thread[tid]->getTC());
     decoder[tid]->moreBytes(instPC, inst->instAddr(), mach_inst);
     assert(decoder[tid]->instReady());
     inst->setStaticInst(decoder[tid]->decode(instPC));
@@ -575,7 +574,7 @@ FetchUnit::squashCacheRequest(CacheReqPtr req_ptr)
 }
 
 void
-FetchUnit::trap(Fault fault, ThreadID tid, DynInstPtr inst)
+FetchUnit::trap(const Fault &fault, ThreadID tid, DynInstPtr inst)
 {
     //@todo: per thread?
     decoder[tid]->reset();