*
*/
-#include <vector>
#include <list>
+#include <vector>
#include "arch/isa_traits.hh"
#include "arch/locked_mem.hh"
#include "arch/utility.hh"
-#include "arch/predecoder.hh"
#include "config/the_isa.hh"
#include "cpu/inorder/resources/cache_unit.hh"
#include "cpu/inorder/resources/fetch_unit.hh"
-#include "cpu/inorder/pipeline_traits.hh"
#include "cpu/inorder/cpu.hh"
+#include "cpu/inorder/pipeline_traits.hh"
#include "cpu/inorder/resource_pool.hh"
+#include "debug/Activity.hh"
+#include "debug/InOrderCachePort.hh"
+#include "debug/InOrderStall.hh"
+#include "debug/RefCount.hh"
+#include "debug/ThreadModel.hh"
#include "mem/request.hh"
using namespace std;
using namespace ThePipeline;
FetchUnit::FetchUnit(string res_name, int res_id, int res_width,
- int res_latency, InOrderCPU *_cpu,
+ Cycles res_latency, InOrderCPU *_cpu,
ThePipeline::Params *params)
: CacheUnit(res_name, res_id, res_width, res_latency, _cpu, params),
- instSize(sizeof(TheISA::MachInst)), fetchBuffSize(params->fetchBuffSize),
- predecoder(NULL)
-{ }
+ instSize(sizeof(TheISA::MachInst)), fetchBuffSize(params->fetchBuffSize)
+{
+ for (int tid = 0; tid < MaxThreads; tid++)
+ decoder[tid] = new Decoder;
+}
+
+FetchUnit::~FetchUnit()
+{
+ std::list<FetchBlock*>::iterator fetch_it = fetchBuffer.begin();
+ std::list<FetchBlock*>::iterator end_it = fetchBuffer.end();
+ while (fetch_it != end_it) {
+ delete (*fetch_it)->block;
+ delete *fetch_it;
+ fetch_it++;
+ }
+ fetchBuffer.clear();
+
+
+ std::list<FetchBlock*>::iterator pend_it = pendingFetch.begin();
+ std::list<FetchBlock*>::iterator pend_end = pendingFetch.end();
+ while (pend_it != pend_end) {
+ if ((*pend_it)->block) {
+ delete (*pend_it)->block;
+ }
+
+ delete *pend_it;
+ pend_it++;
+ }
+ pendingFetch.clear();
+}
void
FetchUnit::createMachInst(std::list<FetchBlock*>::iterator fetch_it,
DynInstPtr inst)
{
- ExtMachInst ext_inst;
Addr block_addr = cacheBlockAlign(inst->getMemAddr());
Addr fetch_addr = inst->getMemAddr();
unsigned fetch_offset = (fetch_addr - block_addr) / instSize;
MachInst mach_inst =
TheISA::gtoh(fetchInsts[fetch_offset]);
- predecoder.setTC(cpu->thread[tid]->getTC());
- predecoder.moreBytes(instPC, inst->instAddr(), mach_inst);
- ext_inst = predecoder.getExtMachInst(instPC);
-
+ decoder[tid]->moreBytes(instPC, inst->instAddr(), mach_inst);
+ assert(decoder[tid]->instReady());
+ inst->setStaticInst(decoder[tid]->decode(instPC));
inst->pcState(instPC);
- inst->setMachInst(ext_inst);
-}
-
-int
-FetchUnit::getSlot(DynInstPtr inst)
-{
- if (tlbBlocked[inst->threadNumber]) {
- return -1;
- }
-
- if (!inst->validMemAddr()) {
- panic("[tid:%i][sn:%i] Mem. Addr. must be set before requesting "
- "cache access\n", inst->readTid(), inst->seqNum);
- }
-
- int new_slot = Resource::getSlot(inst);
-
- if (new_slot == -1)
- return -1;
-
- inst->memTime = curTick();
- return new_slot;
}
void
{
ThreadID tid = inst->readTid();
Addr aligned_addr = cacheBlockAlign(inst->getMemAddr());
-
- inst->fetchMemReq =
+ if (cache_req->memReq == NULL) {
+ cache_req->memReq =
new Request(tid, aligned_addr, acc_size, flags,
- inst->instAddr(), cpu->readCpuId(), tid);
-
- cache_req->memReq = inst->fetchMemReq;
+ cpu->instMasterId(), inst->instAddr(), cpu->readCpuId(),
+ tid);
+ DPRINTF(InOrderCachePort, "[sn:%i] Created memReq @%x, ->%x\n",
+ inst->seqNum, &cache_req->memReq, cache_req->memReq);
+ }
}
std::list<FetchUnit::FetchBlock*>::iterator
}
}
+int
+FetchUnit::blocksInUse()
+{
+ std::list<FetchBlock*>::iterator fetch_it = fetchBuffer.begin();
+ std::list<FetchBlock*>::iterator end_it = fetchBuffer.end();
+
+ int cnt = 0;
+ while (fetch_it != end_it) {
+ if ((*fetch_it)->cnt > 0)
+ cnt++;
+
+ fetch_it++;
+ }
+
+ return cnt;
+}
+
+void
+FetchUnit::clearFetchBuffer()
+{
+ std::list<FetchBlock*>::iterator fetch_it = fetchBuffer.begin();
+ std::list<FetchBlock*>::iterator end_it = fetchBuffer.end();
+
+ while (fetch_it != end_it) {
+ if ((*fetch_it)->block) {
+ delete [] (*fetch_it)->block;
+ }
+ delete *fetch_it;
+ fetch_it++;
+ }
+ fetchBuffer.clear();
+}
+
void
FetchUnit::execute(int slot_num)
{
Addr block_addr = cacheBlockAlign(inst->getMemAddr());
int asid = cpu->asid[tid];
- inst->fault = NoFault;
+ if (inst->fault != NoFault) {
+ DPRINTF(InOrderCachePort,
+ "[tid:%i]: [sn:%i]: Detected %s fault @ %x. Forwarding to "
+ "next stage.\n", tid, inst->seqNum, inst->fault->name(),
+ cacheBlockAlign(inst->getMemAddr()));
+ finishCacheUnitReq(inst, cache_req);
+ return;
+ }
switch (cache_req->cmd)
{
// Check to see if we've already got this request buffered
// or pending to be buffered
bool do_fetch = true;
+ int total_pending = pendingFetch.size() + blocksInUse();
+
std::list<FetchBlock*>::iterator pending_it;
pending_it = findBlock(pendingFetch, asid, block_addr);
if (pending_it != pendingFetch.end()) {
DPRINTF(InOrderCachePort, "%08p is a pending fetch block "
"(pending:%i).\n", block_addr,
(*pending_it)->cnt);
- } else if (pendingFetch.size() < fetchBuffSize) {
+ } else if (total_pending < fetchBuffSize) {
std::list<FetchBlock*>::iterator buff_it;
buff_it = findBlock(fetchBuffer, asid, block_addr);
- if (buff_it != fetchBuffer.end()) {
+ if (buff_it != fetchBuffer.end()) {
(*buff_it)->cnt++;
do_fetch = false;
- DPRINTF(InOrderCachePort, "%08p is in fetch buffer"
+ DPRINTF(InOrderCachePort, "%08p is in fetch buffer "
"(pending:%i).\n", block_addr, (*buff_it)->cnt);
}
}
// Check to see if there is room in the fetchbuffer for this instruction.
// If not, block this request.
- if (pendingFetch.size() >= fetchBuffSize) {
+ if (total_pending >= fetchBuffSize) {
DPRINTF(InOrderCachePort, "No room available in fetch buffer.\n");
- cache_req->done();
+ cache_req->done(false);
return;
}
- doTLBAccess(inst, cache_req, cacheBlkSize, 0, TheISA::TLB::Execute);
+ doTLBAccess(inst, cache_req, cacheBlkSize, Request::INST_FETCH, TheISA::TLB::Execute);
if (inst->fault == NoFault) {
DPRINTF(InOrderCachePort,
if (cache_req->isMemAccPending()) {
pendingFetch.push_back(new FetchBlock(asid, block_addr));
+
+ // mark replacement block
}
}
}
case CompleteFetch:
+ if (inst->fault != NoFault) {
+ DPRINTF(InOrderCachePort,
+ "[tid:%i]: [sn:%i]: Detected %s fault @ %x. Forwarding to "
+ "next stage.\n", tid, inst->seqNum, inst->fault->name(),
+ inst->getMemAddr());
+ finishCacheUnitReq(inst, cache_req);
+ return;
+ }
+
if (cache_req->fetchBufferFill) {
// Block request if it's depending on a previous fetch, but it hasnt made it yet
std::list<FetchBlock*>::iterator fetch_it = findBlock(fetchBuffer, asid, block_addr);
return;
}
+ delete [] (*repl_it)->block;
+ delete *repl_it;
fetchBuffer.erase(repl_it);
}
inst->unsetMemAddr();
- delete cache_req->dataPkt;
-
cache_req->done();
} else {
DPRINTF(InOrderCachePort,
FetchUnit::processCacheCompletion(PacketPtr pkt)
{
// Cast to correct packet type
+ // @todo: use pkt Sender state here to be consistent with other
+ // cpu models
CacheReqPacket* cache_pkt = dynamic_cast<CacheReqPacket*>(pkt);
assert(cache_pkt);
- if (cache_pkt->cacheReq->isSquashed()) {
- DPRINTF(InOrderCachePort,
- "Ignoring completion of squashed access, [tid:%i] [sn:%i]\n",
- cache_pkt->cacheReq->getInst()->readTid(),
- cache_pkt->cacheReq->getInst()->seqNum);
- DPRINTF(RefCount,
- "Ignoring completion of squashed access, [tid:%i] [sn:%i]\n",
- cache_pkt->cacheReq->getTid(),
- cache_pkt->cacheReq->seqNum);
-
- cache_pkt->cacheReq->done();
- cache_pkt->cacheReq->freeSlot();
- delete cache_pkt;
-
- cpu->wakeCPU();
+ DPRINTF(InOrderCachePort, "Finished request for %x\n",
+ cache_pkt->getAddr());
+
+ if (processSquash(cache_pkt))
return;
- }
Addr block_addr = cacheBlockAlign(cache_pkt->cacheReq->
getInst()->getMemAddr());
block_addr);
if (buff_it != fetchBuffer.end()) {
(*buff_it)->cnt--;
- DPRINTF(InOrderCachePort, "[sn:%i] Removing Pending Fetch "
- "for Buffer block %08p (cnt=%i)\n", inst->seqNum,
+ DPRINTF(InOrderCachePort, "[sn:%i] Removing Pending Access "
+ "for Fetch Buffer block %08p (cnt=%i)\n", inst->seqNum,
block_addr, (*buff_it)->cnt);
+ assert((*buff_it)->cnt >= 0);
} else {
std::list<FetchBlock*>::iterator block_it = findBlock(pendingFetch,
asid,
block_addr);
if (block_it != pendingFetch.end()) {
(*block_it)->cnt--;
+ DPRINTF(InOrderCachePort, "[sn:%i] Removing Pending Access "
+ "for Pending Buffer Block %08p (cnt=%i)\n",
+ inst->seqNum,
+ block_addr, (*block_it)->cnt);
+ assert((*block_it)->cnt >= 0);
if ((*block_it)->cnt == 0) {
- DPRINTF(InOrderCachePort, "[sn:%i] Removing Pending Fetch "
- "for block %08p (cnt=%i)\n", inst->seqNum,
- block_addr, (*block_it)->cnt);
+ if ((*block_it)->block) {
+ delete [] (*block_it)->block;
+ }
+ delete *block_it;
pendingFetch.erase(block_it);
}
}
CacheUnit::squashCacheRequest(req_ptr);
}
+void
+FetchUnit::trap(const Fault &fault, ThreadID tid, DynInstPtr inst)
+{
+ //@todo: per thread?
+ decoder[tid]->reset();
+
+ //@todo: squash using dummy inst seq num
+ squash(NULL, NumStages - 1, 0, tid);
+
+ //@todo: make sure no blocks are in use
+ assert(blocksInUse() == 0);
+ assert(pendingFetch.size() == 0);
+
+ //@todo: clear pendingFetch and fetchBuffer
+ clearFetchBuffer();
+}
projects / gem5.git / blobdiff