cpu: Update DRAM traffic gen

[gem5.git] / src / cpu / inorder / resources / fetch_unit.cc

diff --git a/src/cpu/inorder/resources/fetch_unit.cc b/src/cpu/inorder/resources/fetch_unit.cc
index 85411ae28a599d9b2a582f12f7eb2c7a6976d2e4..6892688b2828b83391ea405b628741ee4c43a419 100644 (file)
--- a/src/cpu/inorder/resources/fetch_unit.cc
+++ b/src/cpu/inorder/resources/fetch_unit.cc
@@ -34,7 +34,6 @@
 
 #include "arch/isa_traits.hh"
 #include "arch/locked_mem.hh"
-#include "arch/predecoder.hh"
 #include "arch/utility.hh"
 #include "config/the_isa.hh"
 #include "cpu/inorder/resources/cache_unit.hh"
@@ -54,12 +53,14 @@ using namespace TheISA;
 using namespace ThePipeline;
 
 FetchUnit::FetchUnit(string res_name, int res_id, int res_width,
-                     int res_latency, InOrderCPU *_cpu,
+                     Cycles res_latency, InOrderCPU *_cpu,
                      ThePipeline::Params *params)
     : CacheUnit(res_name, res_id, res_width, res_latency, _cpu, params),
-      instSize(sizeof(TheISA::MachInst)), fetchBuffSize(params->fetchBuffSize),
-      predecoder(NULL)
-{ }
+      instSize(sizeof(TheISA::MachInst)), fetchBuffSize(params->fetchBuffSize)
+{
+    for (int tid = 0; tid < MaxThreads; tid++)
+        decoder[tid] = new Decoder;
+}
 
 FetchUnit::~FetchUnit()
 {
@@ -90,7 +91,6 @@ void
 FetchUnit::createMachInst(std::list<FetchBlock*>::iterator fetch_it,
                           DynInstPtr inst)
 {
-    ExtMachInst ext_inst;
     Addr block_addr = cacheBlockAlign(inst->getMemAddr());
     Addr fetch_addr = inst->getMemAddr();
     unsigned fetch_offset = (fetch_addr - block_addr) / instSize;
@@ -109,13 +109,10 @@ FetchUnit::createMachInst(std::list<FetchBlock*>::iterator fetch_it,
     MachInst mach_inst =
         TheISA::gtoh(fetchInsts[fetch_offset]);
 
-    predecoder.setTC(cpu->thread[tid]->getTC());
-    predecoder.moreBytes(instPC, inst->instAddr(), mach_inst);
-    assert(predecoder.extMachInstReady());
-    ext_inst = predecoder.getExtMachInst(instPC);
-
+    decoder[tid]->moreBytes(instPC, inst->instAddr(), mach_inst);
+    assert(decoder[tid]->instReady());
+    inst->setStaticInst(decoder[tid]->decode(instPC));
     inst->pcState(instPC);
-    inst->setMachInst(ext_inst);
 }
 
 void
@@ -157,7 +154,8 @@ FetchUnit::setupMemRequest(DynInstPtr inst, CacheReqPtr cache_req,
     if (cache_req->memReq == NULL) {
         cache_req->memReq =
             new Request(tid, aligned_addr, acc_size, flags,
-                        inst->instAddr(), cpu->readCpuId(), tid);
+                        cpu->instMasterId(), inst->instAddr(), cpu->readCpuId(),
+                        tid);
         DPRINTF(InOrderCachePort, "[sn:%i] Created memReq @%x, ->%x\n",
                 inst->seqNum, &cache_req->memReq, cache_req->memReq);
     }
@@ -230,6 +228,22 @@ FetchUnit::blocksInUse()
     return cnt;
 }
 
+void
+FetchUnit::clearFetchBuffer()
+{
+    std::list<FetchBlock*>::iterator fetch_it = fetchBuffer.begin();
+    std::list<FetchBlock*>::iterator end_it = fetchBuffer.end();
+
+    while (fetch_it != end_it) {
+        if ((*fetch_it)->block) {
+            delete [] (*fetch_it)->block;
+        }
+        delete *fetch_it;
+        fetch_it++;
+    }
+    fetchBuffer.clear();
+}
+
 void
 FetchUnit::execute(int slot_num)
 {
@@ -560,8 +574,18 @@ FetchUnit::squashCacheRequest(CacheReqPtr req_ptr)
 }
 
 void
-FetchUnit::trap(Fault fault, ThreadID tid, DynInstPtr inst)
+FetchUnit::trap(const Fault &fault, ThreadID tid, DynInstPtr inst)
 {
     //@todo: per thread?
-    predecoder.reset();
+    decoder[tid]->reset();
+
+    //@todo: squash using dummy inst seq num
+    squash(NULL, NumStages - 1, 0, tid);
+
+    //@todo: make sure no blocks are in use
+    assert(blocksInUse() == 0);
+    assert(pendingFetch.size() == 0);
+
+    //@todo: clear pendingFetch and fetchBuffer
+    clearFetchBuffer();
 }