#include "arch/isa_traits.hh"
#include "arch/locked_mem.hh"
-#include "arch/predecoder.hh"
#include "arch/utility.hh"
#include "config/the_isa.hh"
#include "cpu/inorder/resources/cache_unit.hh"
using namespace ThePipeline;
FetchUnit::FetchUnit(string res_name, int res_id, int res_width,
- int res_latency, InOrderCPU *_cpu,
+ Cycles res_latency, InOrderCPU *_cpu,
ThePipeline::Params *params)
: CacheUnit(res_name, res_id, res_width, res_latency, _cpu, params),
instSize(sizeof(TheISA::MachInst)), fetchBuffSize(params->fetchBuffSize)
{
for (int tid = 0; tid < MaxThreads; tid++)
- predecoder[tid] = new Predecoder(NULL);
+ decoder[tid] = new Decoder;
}
FetchUnit::~FetchUnit()
FetchUnit::createMachInst(std::list<FetchBlock*>::iterator fetch_it,
DynInstPtr inst)
{
- ExtMachInst ext_inst;
Addr block_addr = cacheBlockAlign(inst->getMemAddr());
Addr fetch_addr = inst->getMemAddr();
unsigned fetch_offset = (fetch_addr - block_addr) / instSize;
MachInst mach_inst =
TheISA::gtoh(fetchInsts[fetch_offset]);
- predecoder[tid]->setTC(cpu->thread[tid]->getTC());
- predecoder[tid]->moreBytes(instPC, inst->instAddr(), mach_inst);
- assert(predecoder[tid]->extMachInstReady());
- ext_inst = predecoder[tid]->getExtMachInst(instPC);
-
+ decoder[tid]->moreBytes(instPC, inst->instAddr(), mach_inst);
+ assert(decoder[tid]->instReady());
+ inst->setStaticInst(decoder[tid]->decode(instPC));
inst->pcState(instPC);
- inst->setMachInst(ext_inst);
}
void
if (cache_req->memReq == NULL) {
cache_req->memReq =
new Request(tid, aligned_addr, acc_size, flags,
- inst->instAddr(), cpu->readCpuId(), tid);
+ cpu->instMasterId(), inst->instAddr(), cpu->readCpuId(),
+ tid);
DPRINTF(InOrderCachePort, "[sn:%i] Created memReq @%x, ->%x\n",
inst->seqNum, &cache_req->memReq, cache_req->memReq);
}
}
void
-FetchUnit::trap(Fault fault, ThreadID tid, DynInstPtr inst)
+FetchUnit::trap(const Fault &fault, ThreadID tid, DynInstPtr inst)
{
//@todo: per thread?
- predecoder[tid]->reset();
+ decoder[tid]->reset();
//@todo: squash using dummy inst seq num
squash(NULL, NumStages - 1, 0, tid);