#include "arch/isa_traits.hh"
#include "arch/locked_mem.hh"
-#include "arch/predecoder.hh"
#include "arch/utility.hh"
#include "config/the_isa.hh"
#include "cpu/inorder/resources/cache_unit.hh"
using namespace ThePipeline;
FetchUnit::FetchUnit(string res_name, int res_id, int res_width,
- int res_latency, InOrderCPU *_cpu,
+ Cycles res_latency, InOrderCPU *_cpu,
ThePipeline::Params *params)
: CacheUnit(res_name, res_id, res_width, res_latency, _cpu, params),
- instSize(sizeof(TheISA::MachInst)), fetchBuffSize(params->fetchBuffSize),
- predecoder(NULL)
-{ }
+ instSize(sizeof(TheISA::MachInst)), fetchBuffSize(params->fetchBuffSize)
+{
+ for (int tid = 0; tid < MaxThreads; tid++)
+ decoder[tid] = new Decoder;
+}
FetchUnit::~FetchUnit()
{
FetchUnit::createMachInst(std::list<FetchBlock*>::iterator fetch_it,
DynInstPtr inst)
{
- ExtMachInst ext_inst;
Addr block_addr = cacheBlockAlign(inst->getMemAddr());
Addr fetch_addr = inst->getMemAddr();
unsigned fetch_offset = (fetch_addr - block_addr) / instSize;
MachInst mach_inst =
TheISA::gtoh(fetchInsts[fetch_offset]);
- predecoder.setTC(cpu->thread[tid]->getTC());
- predecoder.moreBytes(instPC, inst->instAddr(), mach_inst);
- assert(predecoder.extMachInstReady());
- ext_inst = predecoder.getExtMachInst(instPC);
-
+ decoder[tid]->moreBytes(instPC, inst->instAddr(), mach_inst);
+ assert(decoder[tid]->instReady());
+ inst->setStaticInst(decoder[tid]->decode(instPC));
inst->pcState(instPC);
- inst->setMachInst(ext_inst);
}
void
if (cache_req->memReq == NULL) {
cache_req->memReq =
new Request(tid, aligned_addr, acc_size, flags,
- inst->instAddr(), cpu->readCpuId(), tid);
+ cpu->instMasterId(), inst->instAddr(), cpu->readCpuId(),
+ tid);
DPRINTF(InOrderCachePort, "[sn:%i] Created memReq @%x, ->%x\n",
inst->seqNum, &cache_req->memReq, cache_req->memReq);
}
return cnt;
}
+void
+FetchUnit::clearFetchBuffer()
+{
+ std::list<FetchBlock*>::iterator fetch_it = fetchBuffer.begin();
+ std::list<FetchBlock*>::iterator end_it = fetchBuffer.end();
+
+ while (fetch_it != end_it) {
+ if ((*fetch_it)->block) {
+ delete [] (*fetch_it)->block;
+ }
+ delete *fetch_it;
+ fetch_it++;
+ }
+ fetchBuffer.clear();
+}
+
void
FetchUnit::execute(int slot_num)
{
Addr block_addr = cacheBlockAlign(inst->getMemAddr());
int asid = cpu->asid[tid];
- inst->fault = NoFault;
+ if (inst->fault != NoFault) {
+ DPRINTF(InOrderCachePort,
+ "[tid:%i]: [sn:%i]: Detected %s fault @ %x. Forwarding to "
+ "next stage.\n", tid, inst->seqNum, inst->fault->name(),
+ cacheBlockAlign(inst->getMemAddr()));
+ finishCacheUnitReq(inst, cache_req);
+ return;
+ }
switch (cache_req->cmd)
{
return;
}
- doTLBAccess(inst, cache_req, cacheBlkSize, 0, TheISA::TLB::Execute);
+ doTLBAccess(inst, cache_req, cacheBlkSize, Request::INST_FETCH, TheISA::TLB::Execute);
if (inst->fault == NoFault) {
DPRINTF(InOrderCachePort,
}
case CompleteFetch:
+ if (inst->fault != NoFault) {
+ DPRINTF(InOrderCachePort,
+ "[tid:%i]: [sn:%i]: Detected %s fault @ %x. Forwarding to "
+ "next stage.\n", tid, inst->seqNum, inst->fault->name(),
+ inst->getMemAddr());
+ finishCacheUnitReq(inst, cache_req);
+ return;
+ }
+
if (cache_req->fetchBufferFill) {
// Block request if it's depending on a previous fetch, but it hasnt made it yet
std::list<FetchBlock*>::iterator fetch_it = findBlock(fetchBuffer, asid, block_addr);
}
void
-FetchUnit::trap(Fault fault, ThreadID tid, DynInstPtr inst)
+FetchUnit::trap(const Fault &fault, ThreadID tid, DynInstPtr inst)
{
//@todo: per thread?
- predecoder.reset();
+ decoder[tid]->reset();
+
+ //@todo: squash using dummy inst seq num
+ squash(NULL, NumStages - 1, 0, tid);
+
+ //@todo: make sure no blocks are in use
+ assert(blocksInUse() == 0);
+ assert(pendingFetch.size() == 0);
+
+ //@todo: clear pendingFetch and fetchBuffer
+ clearFetchBuffer();
}