cpu: Update DRAM traffic gen

[gem5.git] / src / cpu / inorder / resources / fetch_unit.hh

diff --git a/src/cpu/inorder/resources/fetch_unit.hh b/src/cpu/inorder/resources/fetch_unit.hh
index 035f3f4a176945ed401b86a43c2333c7462054e7..d72721009b198ac37135a15836758066e5fb20f7 100644 (file)
--- a/src/cpu/inorder/resources/fetch_unit.hh
+++ b/src/cpu/inorder/resources/fetch_unit.hh
@@ -32,17 +32,17 @@
 #ifndef __CPU_INORDER_FETCH_UNIT_HH__
 #define __CPU_INORDER_FETCH_UNIT_HH__
 
-#include <vector>
 #include <list>
 #include <string>
+#include <vector>
 
-#include "arch/predecoder.hh"
+#include "arch/decoder.hh"
 #include "arch/tlb.hh"
 #include "config/the_isa.hh"
+#include "cpu/inorder/resources/cache_unit.hh"
 #include "cpu/inorder/inorder_dyn_inst.hh"
 #include "cpu/inorder/pipeline_traits.hh"
 #include "cpu/inorder/resource.hh"
-#include "cpu/inorder/resources/cache_unit.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 #include "mem/port.hh"
@@ -53,7 +53,10 @@ class FetchUnit : public CacheUnit
 {
   public:
     FetchUnit(std::string res_name, int res_id, int res_width,
-              int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
+              Cycles res_latency, InOrderCPU *_cpu,
+              ThePipeline::Params *params);
+
+    virtual ~FetchUnit();
 
     typedef ThePipeline::DynInstPtr DynInstPtr;
     typedef TheISA::ExtMachInst ExtMachInst;
@@ -81,11 +84,13 @@ class FetchUnit : public CacheUnit
                                 int res_idx, int slot_num,
                                 unsigned cmd);
 
-    int getSlot(DynInstPtr inst);
-
     /** Executes one of the commands from the "Command" enum */
     void execute(int slot_num);
 
+    void trap(const Fault &fault, ThreadID tid, DynInstPtr inst);
+
+    TheISA::Decoder *decoder[ThePipeline::MaxThreads];
+
   private:
     void squashCacheRequest(CacheReqPtr req_ptr);
 
@@ -116,12 +121,14 @@ class FetchUnit : public CacheUnit
 
     void markBlockUsed(std::list<FetchBlock*>::iterator block_it);
 
+    int blocksInUse();
+
+    void clearFetchBuffer();
+
     int instSize;
 
     int fetchBuffSize;
 
-    TheISA::Predecoder predecoder;
-
     /** Valid Cache Blocks*/
     std::list<FetchBlock*> fetchBuffer;