cpu: Update DRAM traffic gen

[gem5.git] / src / cpu / inorder / resources / fetch_unit.hh

diff --git a/src/cpu/inorder/resources/fetch_unit.hh b/src/cpu/inorder/resources/fetch_unit.hh
index 257a8c50ac161861b6f2131a183267c5144feda7..d72721009b198ac37135a15836758066e5fb20f7 100644 (file)
--- a/src/cpu/inorder/resources/fetch_unit.hh
+++ b/src/cpu/inorder/resources/fetch_unit.hh
@@ -32,17 +32,17 @@
 #ifndef __CPU_INORDER_FETCH_UNIT_HH__
 #define __CPU_INORDER_FETCH_UNIT_HH__
 
-#include <vector>
 #include <list>
 #include <string>
+#include <vector>
 
-#include "arch/predecoder.hh"
+#include "arch/decoder.hh"
 #include "arch/tlb.hh"
 #include "config/the_isa.hh"
+#include "cpu/inorder/resources/cache_unit.hh"
 #include "cpu/inorder/inorder_dyn_inst.hh"
 #include "cpu/inorder/pipeline_traits.hh"
 #include "cpu/inorder/resource.hh"
-#include "cpu/inorder/resources/cache_unit.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 #include "mem/port.hh"
@@ -51,31 +51,51 @@
 
 class FetchUnit : public CacheUnit
 {
-  public:
-    typedef ThePipeline::DynInstPtr DynInstPtr;
-
   public:
     FetchUnit(std::string res_name, int res_id, int res_width,
-              int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
+              Cycles res_latency, InOrderCPU *_cpu,
+              ThePipeline::Params *params);
+
+    virtual ~FetchUnit();
+
+    typedef ThePipeline::DynInstPtr DynInstPtr;
+    typedef TheISA::ExtMachInst ExtMachInst;
+
+    struct FetchBlock {
+        int asid;
+        Addr addr;
+        uint8_t *block;
+        short cnt;
+        bool valid;
+
+        FetchBlock(int _asid, Addr _addr)
+            : asid(_asid), addr(_addr), block(NULL), cnt(1), valid(false)
+        { }
+    };
 
-    /** Actions that this resources can take on an instruction */
+    /** Actions that this resource can take on an instruction */
     enum Command {
         InitiateFetch,
         CompleteFetch
     };
 
-  public:
+
     ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
                                 int res_idx, int slot_num,
                                 unsigned cmd);
 
-    int getSlot(DynInstPtr inst);
-
     /** Executes one of the commands from the "Command" enum */
     void execute(int slot_num);
 
-    void squash(DynInstPtr inst, int stage_num,
-                InstSeqNum squash_seq_num, ThreadID tid);
+    void trap(const Fault &fault, ThreadID tid, DynInstPtr inst);
+
+    TheISA::Decoder *decoder[ThePipeline::MaxThreads];
+
+  private:
+    void squashCacheRequest(CacheReqPtr req_ptr);
+
+    void createMachInst(std::list<FetchBlock*>::iterator fetch_it,
+                        DynInstPtr inst);
 
     /** After memory request is completed, then turn the fetched data
         into an instruction.
@@ -94,14 +114,26 @@ class FetchUnit : public CacheUnit
 
     void removeAddrDependency(DynInstPtr inst);
 
-  public:
-    /** The mem line being fetched. */
-    uint8_t *fetchData[ThePipeline::MaxThreads];
+    std::list<FetchBlock*>::iterator findReplacementBlock();
+    std::list<FetchBlock*>::iterator findBlock(std::list<FetchBlock*>
+                                               &fetch_blocks, int asid,
+                                               Addr block_addr);
+
+    void markBlockUsed(std::list<FetchBlock*>::iterator block_it);
+
+    int blocksInUse();
+
+    void clearFetchBuffer();
+
+    int instSize;
+
+    int fetchBuffSize;
 
+    /** Valid Cache Blocks*/
+    std::list<FetchBlock*> fetchBuffer;
 
-    /** The Addr of the cacheline that has been loaded. */
-    //Addr cacheBlockAddr[ThePipeline::MaxThreads];
-    //unsigned fetchOffset[ThePipeline::MaxThreads];
+    /** Cache lines that are pending */
+    std::list<FetchBlock*> pendingFetch;
 };
 
 #endif //__CPU_FETCH_UNIT_HH__