cpu: Update DRAM traffic gen

[gem5.git] / src / cpu / inorder / resources / fetch_unit.hh

diff --git a/src/cpu/inorder/resources/fetch_unit.hh b/src/cpu/inorder/resources/fetch_unit.hh
index 6d734d7e6a6ebb0d8d6f2a4182ebf6585742802b..d72721009b198ac37135a15836758066e5fb20f7 100644 (file)
--- a/src/cpu/inorder/resources/fetch_unit.hh
+++ b/src/cpu/inorder/resources/fetch_unit.hh
@@ -36,10 +36,9 @@
 #include <string>
 #include <vector>
 
-#include "arch/predecoder.hh"
+#include "arch/decoder.hh"
 #include "arch/tlb.hh"
 #include "config/the_isa.hh"
-#include "cpu/decode.hh"
 #include "cpu/inorder/resources/cache_unit.hh"
 #include "cpu/inorder/inorder_dyn_inst.hh"
 #include "cpu/inorder/pipeline_traits.hh"
@@ -54,7 +53,8 @@ class FetchUnit : public CacheUnit
 {
   public:
     FetchUnit(std::string res_name, int res_id, int res_width,
-              int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
+              Cycles res_latency, InOrderCPU *_cpu,
+              ThePipeline::Params *params);
 
     virtual ~FetchUnit();
 
@@ -87,9 +87,9 @@ class FetchUnit : public CacheUnit
     /** Executes one of the commands from the "Command" enum */
     void execute(int slot_num);
 
-    void trap(Fault fault, ThreadID tid, DynInstPtr inst);
+    void trap(const Fault &fault, ThreadID tid, DynInstPtr inst);
 
-    Decoder decoder;
+    TheISA::Decoder *decoder[ThePipeline::MaxThreads];
 
   private:
     void squashCacheRequest(CacheReqPtr req_ptr);
@@ -129,8 +129,6 @@ class FetchUnit : public CacheUnit
 
     int fetchBuffSize;
 
-    TheISA::Predecoder *predecoder[ThePipeline::MaxThreads];
-
     /** Valid Cache Blocks*/
     std::list<FetchBlock*> fetchBuffer;