cpu: Update DRAM traffic gen

[gem5.git] / src / cpu / inorder / resources / inst_buffer.cc

diff --git a/src/cpu/inorder/resources/inst_buffer.cc b/src/cpu/inorder/resources/inst_buffer.cc
index 1db618b61b0e12beaf2992435f77f722a292d8fe..19011059fa897d13f61bff27120b1cee692be45b 100644 (file)
--- a/src/cpu/inorder/resources/inst_buffer.cc
+++ b/src/cpu/inorder/resources/inst_buffer.cc
@@ -29,21 +29,23 @@
  *
  */
 
-#include <vector>
 #include <list>
+#include <vector>
 
 #include "arch/isa_traits.hh"
 #include "config/the_isa.hh"
-#include "cpu/inorder/pipeline_traits.hh"
 #include "cpu/inorder/resources/inst_buffer.hh"
 #include "cpu/inorder/cpu.hh"
+#include "cpu/inorder/pipeline_traits.hh"
+#include "debug/InOrderInstBuffer.hh"
+#include "debug/Resource.hh"
 
 using namespace std;
 using namespace TheISA;
 using namespace ThePipeline;
 
 InstBuffer::InstBuffer(string res_name, int res_id, int res_width,
-                       int res_latency, InOrderCPU *_cpu,
+                       Cycles res_latency, InOrderCPU *_cpu,
                        ThePipeline::Params *params)
     : Resource(res_name, res_id, res_width, res_latency, _cpu)
 { }
@@ -62,13 +64,11 @@ InstBuffer::regStats()
 void
 InstBuffer::execute(int slot_idx)
 {
-    ResReqPtr ib_req = reqMap[slot_idx];
+    ResReqPtr ib_req = reqs[slot_idx];
     DynInstPtr inst = ib_req->inst;
     ThreadID tid = inst->readTid();
     int stage_num = ib_req->getStageNum();
 
-    ib_req->fault = NoFault;
-
     switch (ib_req->cmd)
     {
       case ScheduleOrBypass:
@@ -101,19 +101,22 @@ InstBuffer::execute(int slot_idx)
                         inst->seqNum, next_stage);
 
                 // Add to schedule: Insert into buffer in next stage
-                int stage_pri = ThePipeline::getNextPriority(inst,
-                                                             next_stage);
+                int stage_pri = 20;
+                RSkedPtr insert_sked = (stage_num >= ThePipeline::BackEndStartStage) ?
+                    inst->backSked : inst->frontSked;
 
-                inst->resSched.push(new ScheduleEntry(next_stage,
+                insert_sked->push(new ScheduleEntry(next_stage,
                                                       stage_pri,
                                                       id,
                                                       InstBuffer::InsertInst));
 
                 // Add to schedule: Remove from buffer in next next (bypass)
                 // stage
-                stage_pri = ThePipeline::getNextPriority(inst, bypass_stage);
+                stage_pri = 20;
+                RSkedPtr bypass_sked = (stage_num >= ThePipeline::BackEndStartStage) ?
+                    inst->backSked : inst->frontSked;
 
-                inst->resSched.push(new ScheduleEntry(bypass_stage,
+               bypass_sked->push(new ScheduleEntry(bypass_stage,
                                                       stage_pri,
                                                       id,
                                                       InstBuffer::RemoveInst));