#ifndef __CPU_INORDER_MULT_DIV_UNIT_HH__
#define __CPU_INORDER_MULT_DIV_UNIT_HH__
-#include <vector>
#include <list>
#include <string>
+#include <vector>
-#include "cpu/func_unit.hh"
-#include "cpu/op_class.hh"
#include "cpu/inorder/first_stage.hh"
-#include "cpu/inorder/resource.hh"
#include "cpu/inorder/inorder_dyn_inst.hh"
+#include "cpu/inorder/resource.hh"
+#include "cpu/func_unit.hh"
+#include "cpu/op_class.hh"
class MDUEvent;
public:
MultDivUnit(std::string res_name, int res_id, int res_width,
- int res_latency, InOrderCPU *_cpu,
+ Cycles res_latency, InOrderCPU *_cpu,
ThePipeline::Params *params);
public:
* valid mult/div sequence is being maintained
*/
int getSlot(DynInstPtr inst);
-
- int findSlot(DynInstPtr inst);
-
- void freeSlot(int slot_idx);
void init();
void requestAgain(DynInstPtr inst, bool &try_request);
+ void squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num,
+ ThreadID tid);
+
protected:
/** Latency & Repeat Rate for Multiply Insts */
unsigned multRepeatRate;
- unsigned multLatency;
+ Cycles multLatency;
/** Latency & Repeat Rate for 8-bit Divide Insts */
unsigned div8RepeatRate;
- unsigned div8Latency;
+ Cycles div8Latency;
/** Latency & Repeat Rate for 16-bit Divide Insts */
unsigned div16RepeatRate;
- unsigned div16Latency;
+ Cycles div16Latency;
/** Latency & Repeat Rate for 24-bit Divide Insts */
unsigned div24RepeatRate;
- unsigned div24Latency;
+ Cycles div24Latency;
/** Latency & Repeat Rate for 32-bit Divide Insts */
unsigned div32RepeatRate;
- unsigned div32Latency;
+ Cycles div32Latency;
/** Last cycle that MDU was used */
Tick lastMDUCycle;