cpu: Update DRAM traffic gen

[gem5.git] / src / cpu / inorder / resources / tlb_unit.cc

diff --git a/src/cpu/inorder/resources/tlb_unit.cc b/src/cpu/inorder/resources/tlb_unit.cc
index 37aec2209171660ef64f4de31591eb5a00919703..c2619f15e3cb06903bb1af09ef9a498a95dd42fb 100644 (file)
--- a/src/cpu/inorder/resources/tlb_unit.cc
+++ b/src/cpu/inorder/resources/tlb_unit.cc
@@ -29,22 +29,23 @@
  *
  */
 
-#include <vector>
 #include <list>
+#include <vector>
 
 #include "arch/isa_traits.hh"
 #include "config/the_isa.hh"
-#include "cpu/inorder/pipeline_traits.hh"
-#include "cpu/inorder/first_stage.hh"
 #include "cpu/inorder/resources/tlb_unit.hh"
 #include "cpu/inorder/cpu.hh"
+#include "cpu/inorder/first_stage.hh"
+#include "cpu/inorder/pipeline_traits.hh"
 
 using namespace std;
 using namespace TheISA;
 using namespace ThePipeline;
 
 TLBUnit::TLBUnit(string res_name, int res_id, int res_width,
-                 int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params)
+                 Cycles res_latency, InOrderCPU *_cpu,
+                 ThePipeline::Params *params)
 : Resource(res_name, res_id, res_width, res_latency, _cpu)
 {
     // Hard-Code Selection For Now
@@ -109,7 +110,7 @@ TLBUnit::execute(int slot_idx)
 
     DynInstPtr inst = tlb_req->inst;
     ThreadID tid = inst->readTid();
-    int seq_num = inst->seqNum;
+    InstSeqNum seq_num = inst->seqNum;
     int stage_num = tlb_req->getStageNum();
 
     tlb_req->fault = NoFault;