Yet another merge with the main repository.

[gem5.git] / src / cpu / inorder / resources / use_def.hh

diff --git a/src/cpu/inorder/resources/use_def.hh b/src/cpu/inorder/resources/use_def.hh
index 21770cec6d89c75a7be911d6813e0d32853a78b7..9581bc5f58604fd74c6087d0d96d86f6c2060dd2 100644 (file)
--- a/src/cpu/inorder/resources/use_def.hh
+++ b/src/cpu/inorder/resources/use_def.hh
@@ -32,24 +32,26 @@
 #ifndef __CPU_INORDER_USE_DEF_UNIT_HH__
 #define __CPU_INORDER_USE_DEF_UNIT_HH__
 
-#include <vector>
 #include <list>
 #include <string>
+#include <vector>
 
-#include "cpu/func_unit.hh"
 #include "cpu/inorder/first_stage.hh"
-#include "cpu/inorder/resource.hh"
 #include "cpu/inorder/inorder_dyn_inst.hh"
 #include "cpu/inorder/pipeline_traits.hh"
 #include "cpu/inorder/reg_dep_map.hh"
+#include "cpu/inorder/resource.hh"
+#include "cpu/func_unit.hh"
 
 class UseDefUnit : public Resource {
   public:
     typedef ThePipeline::DynInstPtr DynInstPtr;
+    typedef TheISA::RegIndex RegIndex;
 
     enum Command {
         ReadSrcReg,
-        WriteDestReg
+        WriteDestReg,
+        MarkDestRegs
     };
 
   public:
@@ -66,31 +68,23 @@ class UseDefUnit : public Resource {
 
     void execute(int slot_num);
 
-    void squash(DynInstPtr inst, int stage_num,
-                        InstSeqNum squash_seq_num, ThreadID tid);
-
     void updateAfterContextSwitch(DynInstPtr inst, ThreadID tid);    
 
-    const InstSeqNum maxSeqNum;
-
     void regStats();
     
   protected:
     RegDepMap *regDepMap[ThePipeline::MaxThreads];
 
-    /** Outstanding Seq. Num. Trying to Read from Register File */
-    InstSeqNum outReadSeqNum[ThePipeline::MaxThreads];
-
-    InstSeqNum outWriteSeqNum[ThePipeline::MaxThreads];
-
     bool *nonSpecInstActive[ThePipeline::MaxThreads];
-
     InstSeqNum *nonSpecSeqNum[ThePipeline::MaxThreads];
 
-    InstSeqNum floatRegSize[ThePipeline::MaxThreads];
+    bool serializeOnNextInst[ThePipeline::MaxThreads];
+    InstSeqNum serializeAfterSeqNum[ThePipeline::MaxThreads];
 
     Stats::Average uniqueRegsPerSwitch;
-    std::map<unsigned, bool> uniqueRegMap;    
+    std::map<RegIndex, bool> uniqueIntRegMap;
+    std::map<RegIndex, bool> uniqueFloatRegMap;
+    std::map<RegIndex, bool> uniqueMiscRegMap;
 
   public:
     class UseDefRequest : public ResourceRequest {
@@ -115,17 +109,26 @@ class UseDefUnit : public Resource {
     };
 
   protected:
-    /** Register File Reads */
-    Stats::Scalar regFileReads;
+    /** Int. Register File Reads */
+    Stats::Scalar intRegFileReads;
+
+    /** Int. Register File Writes */
+    Stats::Scalar intRegFileWrites;
 
-    /** Register File Writes */
-    Stats::Scalar regFileWrites;
+    /** Int. Register File Total Accesses (Read+Write) */
+    Stats::Formula intRegFileAccs;
+
+    /** Float Register File Reads */
+    Stats::Scalar floatRegFileReads;
+
+    /** Float Register File Writes */
+    Stats::Scalar floatRegFileWrites;
+
+    /** Float Register File Total Accesses (Read+Write) */
+    Stats::Formula floatRegFileAccs;
 
     /** Source Register Forwarding */
     Stats::Scalar regForwards;
-
-    /** Register File Total Accesses (Read+Write) */
-    Stats::Formula regFileAccs;
 };
 
 #endif //__CPU_INORDER_USE_DEF_UNIT_HH__