Yet another merge with the main repository.

[gem5.git] / src / cpu / inorder / resources / use_def.hh

diff --git a/src/cpu/inorder/resources/use_def.hh b/src/cpu/inorder/resources/use_def.hh
index 238591117ce0bdfc310e3b3e24d0316887289775..9581bc5f58604fd74c6087d0d96d86f6c2060dd2 100644 (file)
--- a/src/cpu/inorder/resources/use_def.hh
+++ b/src/cpu/inorder/resources/use_def.hh
@@ -32,56 +32,59 @@
 #ifndef __CPU_INORDER_USE_DEF_UNIT_HH__
 #define __CPU_INORDER_USE_DEF_UNIT_HH__
 
-#include <vector>
 #include <list>
 #include <string>
+#include <vector>
 
-#include "cpu/func_unit.hh"
 #include "cpu/inorder/first_stage.hh"
-#include "cpu/inorder/resource.hh"
 #include "cpu/inorder/inorder_dyn_inst.hh"
 #include "cpu/inorder/pipeline_traits.hh"
 #include "cpu/inorder/reg_dep_map.hh"
+#include "cpu/inorder/resource.hh"
+#include "cpu/func_unit.hh"
 
 class UseDefUnit : public Resource {
   public:
     typedef ThePipeline::DynInstPtr DynInstPtr;
+    typedef TheISA::RegIndex RegIndex;
 
     enum Command {
         ReadSrcReg,
-        WriteDestReg
+        WriteDestReg,
+        MarkDestRegs
     };
 
   public:
     UseDefUnit(std::string res_name, int res_id, int res_width,
-              int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
-    virtual ~UseDefUnit() {}
+               int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
 
-    virtual ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
+    void init();
+
+    ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
                                         int res_idx, int slot_num,
                                         unsigned cmd);
 
-    virtual ResReqPtr findRequest(DynInstPtr inst);
-
-    virtual void execute(int slot_num);
+    ResReqPtr findRequest(DynInstPtr inst);
 
-    virtual void squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, unsigned tid);
+    void execute(int slot_num);
 
-    const InstSeqNum maxSeqNum;
+    void updateAfterContextSwitch(DynInstPtr inst, ThreadID tid);    
 
+    void regStats();
+    
   protected:
     RegDepMap *regDepMap[ThePipeline::MaxThreads];
 
-    /** Outstanding Seq. Num. Trying to Read from Register File */
-    InstSeqNum outReadSeqNum[ThePipeline::MaxThreads];
-
-    InstSeqNum outWriteSeqNum[ThePipeline::MaxThreads];
-
     bool *nonSpecInstActive[ThePipeline::MaxThreads];
-
     InstSeqNum *nonSpecSeqNum[ThePipeline::MaxThreads];
 
-    /** @todo: Add Resource Stats Here */
+    bool serializeOnNextInst[ThePipeline::MaxThreads];
+    InstSeqNum serializeAfterSeqNum[ThePipeline::MaxThreads];
+
+    Stats::Average uniqueRegsPerSwitch;
+    std::map<RegIndex, bool> uniqueIntRegMap;
+    std::map<RegIndex, bool> uniqueFloatRegMap;
+    std::map<RegIndex, bool> uniqueMiscRegMap;
 
   public:
     class UseDefRequest : public ResourceRequest {
@@ -89,14 +92,43 @@ class UseDefUnit : public Resource {
         typedef ThePipeline::DynInstPtr DynInstPtr;
 
       public:
-        UseDefRequest(UseDefUnit *res, DynInstPtr inst, int stage_num, int res_idx,
-                      int slot_num, unsigned cmd, int use_def_idx)
-            : ResourceRequest(res, inst, stage_num, res_idx, slot_num, cmd),
-              useDefIdx(use_def_idx)
+        UseDefRequest(UseDefUnit *res)
+            : ResourceRequest(res)
         { }
 
         int useDefIdx;
+
+        void setRequest(DynInstPtr _inst, int stage_num, int res_idx,
+                        int slot_num, unsigned _cmd, int idx)
+        {
+            useDefIdx = idx;
+
+            ResourceRequest::setRequest(_inst, stage_num, res_idx, slot_num,
+                                        _cmd);
+        }
     };
+
+  protected:
+    /** Int. Register File Reads */
+    Stats::Scalar intRegFileReads;
+
+    /** Int. Register File Writes */
+    Stats::Scalar intRegFileWrites;
+
+    /** Int. Register File Total Accesses (Read+Write) */
+    Stats::Formula intRegFileAccs;
+
+    /** Float Register File Reads */
+    Stats::Scalar floatRegFileReads;
+
+    /** Float Register File Writes */
+    Stats::Scalar floatRegFileWrites;
+
+    /** Float Register File Total Accesses (Read+Write) */
+    Stats::Formula floatRegFileAccs;
+
+    /** Source Register Forwarding */
+    Stats::Scalar regForwards;
 };
 
 #endif //__CPU_INORDER_USE_DEF_UNIT_HH__