arch, cpu: Add support for flattening misc register indexes.

[gem5.git] / src / cpu / inorder / thread_context.hh

diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh
index 0f9b1028ea9e18553b43d64908749798efdd80d7..b1a3610275681511b7293f1e4b324fed93834da3 100644 (file)
--- a/src/cpu/inorder/thread_context.hh
+++ b/src/cpu/inorder/thread_context.hh
@@ -1,4 +1,17 @@
 /*
+ * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2007 MIPS Technologies, Inc.
  * All rights reserved.
  *
@@ -40,6 +53,7 @@
 #include "arch/kernel_stats.hh"
 
 class EndQuiesceEvent;
+class CheckerCPU;
 namespace Kernel {
     class Statistics;
 };
@@ -76,7 +90,17 @@ class InOrderThreadContext : public ThreadContext
     /** @TODO: PERF: Should we bind this to a pointer in constructor? */
     TheISA::TLB *getDTBPtr() { return cpu->getDTBPtr(); }
 
-    Decoder *getDecoderPtr() { return cpu->getDecoderPtr(); }
+    /** Currently InOrder model does not support CheckerCPU, this is
+     *  merely here for supporting compilation of gem5 with the Checker
+     *  as a runtime option
+     */
+    CheckerCPU *getCheckerCpuPtr() { return NULL; }
+
+    TheISA::Decoder *
+    getDecoderPtr()
+    {
+        return cpu->getDecoderPtr(thread->contextId());
+    }
 
     System *getSystemPtr() { return cpu->system; }
 
@@ -107,10 +131,6 @@ class InOrderThreadContext : public ThreadContext
 
     void setNextMicroPC(uint64_t val) { };
 
-    /** Returns a pointer to physical memory. */
-    PhysicalMemory *getPhysMemPtr()
-    { assert(0); return 0; /*return cpu->physmem;*/ }
-
     /** Returns a pointer to this thread's kernel statistics. */
     TheISA::Kernel::Statistics *getKernelStats()
     { return thread->kernelStats; }
@@ -158,13 +178,13 @@ class InOrderThreadContext : public ThreadContext
 
     /** Set the status to Active.  Optional delay indicates number of
      * cycles to wait before beginning execution. */
-    void activate(int delay = 1);
+    void activate(Cycles delay = Cycles(1));
 
     /** Set the status to Suspended. */
-    void suspend(int delay = 0);
+    void suspend(Cycles delay = Cycles(0));
 
     /** Set the status to Halted. */
-    void halt(int delay = 0);
+    void halt(Cycles delay = Cycles(0));
 
     /** Takes over execution of a thread from another CPU. */
     void takeOverFrom(ThreadContext *old_context);
@@ -172,12 +192,6 @@ class InOrderThreadContext : public ThreadContext
     /** Registers statistics associated with this TC. */
     void regStats(const std::string &name);
 
-    /** Serializes state. */
-    void serialize(std::ostream &os);
-
-    /** Unserializes state. */
-    void unserialize(Checkpoint *cp, const std::string &section);
-
     /** Returns this thread's ID number. */
     int getThreadNum() { return thread->threadId(); }
 
@@ -194,6 +208,8 @@ class InOrderThreadContext : public ThreadContext
 
     FloatRegBits readFloatRegBits(int reg_idx);
 
+    CCReg readCCReg(int reg_idx);
+
     uint64_t readRegOtherThread(int misc_reg, ThreadID tid);
 
     /** Sets an integer register to a value. */
@@ -203,6 +219,8 @@ class InOrderThreadContext : public ThreadContext
 
     void setFloatRegBits(int reg_idx, FloatRegBits val);
 
+    void setCCReg(int reg_idx, CCReg val);
+
     void setRegOtherThread(int misc_reg,
                                    const MiscReg &val,
                                    ThreadID tid);
@@ -215,6 +233,12 @@ class InOrderThreadContext : public ThreadContext
     void pcState(const TheISA::PCState &val)
     { cpu->pcState(val, thread->threadId()); }
 
+    /** Needs to be implemented for future CheckerCPU support.
+     *  See O3CPU for examples on how to integrate Checker.
+     */
+    void pcStateNoRecord(const TheISA::PCState &val)
+    {}
+
     Addr instAddr()
     { return cpu->instAddr(thread->threadId()); }
 
@@ -241,12 +265,18 @@ class InOrderThreadContext : public ThreadContext
     void setMiscReg(int misc_reg, const MiscReg &val);
 
     int flattenIntIndex(int reg)
-    { return cpu->isa[thread->threadId()].flattenIntIndex(reg); }
+    { return cpu->isa[thread->threadId()]->flattenIntIndex(reg); }
 
     int flattenFloatIndex(int reg)
-    { return cpu->isa[thread->threadId()].flattenFloatIndex(reg); }
+    { return cpu->isa[thread->threadId()]->flattenFloatIndex(reg); }
+
+    int flattenCCIndex(int reg)
+    { return cpu->isa[thread->threadId()]->flattenCCIndex(reg); }
+
+    int flattenMiscIndex(int reg)
+    { return cpu->isa[thread->threadId()]->flattenMiscIndex(reg); }
 
-    void activateContext(int delay)
+    void activateContext(Cycles delay)
     { cpu->activateContext(thread->threadId(), delay); }
 
     void deallocateContext()
@@ -279,6 +309,18 @@ class InOrderThreadContext : public ThreadContext
     void changeRegFileContext(unsigned param,
                                       unsigned val)
     { panic("Not supported!"); }
+
+    uint64_t readIntRegFlat(int idx);
+    void setIntRegFlat(int idx, uint64_t val);
+
+    FloatReg readFloatRegFlat(int idx);
+    void setFloatRegFlat(int idx, FloatReg val);
+
+    FloatRegBits readFloatRegBitsFlat(int idx);
+    void setFloatRegBitsFlat(int idx, FloatRegBits val);
+
+    CCReg readCCRegFlat(int idx);
+    void setCCRegFlat(int idx, CCReg val);
 };
 
 #endif