/*
+ * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2007 MIPS Technologies, Inc.
* All rights reserved.
*
#include "arch/kernel_stats.hh"
class EndQuiesceEvent;
+class CheckerCPU;
namespace Kernel {
class Statistics;
};
-class TranslatingPort;
-
/**
* Derived ThreadContext class for use with the InOrderCPU. It
* provides the interface for any external objects to access a
/** @TODO: PERF: Should we bind this to a pointer in constructor? */
TheISA::TLB *getDTBPtr() { return cpu->getDTBPtr(); }
- Decoder *getDecoderPtr() { return cpu->getDecoderPtr(); }
+ /** Currently InOrder model does not support CheckerCPU, this is
+ * merely here for supporting compilation of gem5 with the Checker
+ * as a runtime option
+ */
+ CheckerCPU *getCheckerCpuPtr() { return NULL; }
+
+ TheISA::Decoder *
+ getDecoderPtr()
+ {
+ return cpu->getDecoderPtr(thread->contextId());
+ }
System *getSystemPtr() { return cpu->system; }
void setNextMicroPC(uint64_t val) { };
-#if FULL_SYSTEM
- /** Returns a pointer to physical memory. */
- PhysicalMemory *getPhysMemPtr()
- { assert(0); return 0; /*return cpu->physmem;*/ }
-
/** Returns a pointer to this thread's kernel statistics. */
TheISA::Kernel::Statistics *getKernelStats()
{ return thread->kernelStats; }
- void connectMemPorts(ThreadContext *tc)
- { thread->connectMemPorts(tc); }
+ PortProxy &getPhysProxy() { return thread->getPhysProxy(); }
+
+ FSTranslatingPortProxy &getVirtProxy();
+
+ void initMemProxies(ThreadContext *tc)
+ { thread->initMemProxies(tc); }
/** Dumps the function profiling information.
* @todo: Implement.
{
return this->thread->quiesceEvent;
}
-#else
- /** Returns a pointer to this thread's process. */
- Process *getProcessPtr() { return thread->getProcessPtr(); }
-#endif
- TranslatingPort *getMemPort() { return thread->getMemPort(); }
+ SETranslatingPortProxy &getMemProxy() { return thread->getMemProxy(); }
- VirtualPort *getVirtPort();
- FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
+ /** Returns a pointer to this thread's process. */
+ Process *getProcessPtr() { return thread->getProcessPtr(); }
/** Returns this thread's status. */
Status status() const { return thread->status(); }
/** Set the status to Active. Optional delay indicates number of
* cycles to wait before beginning execution. */
- void activate(int delay = 1);
+ void activate(Cycles delay = Cycles(1));
/** Set the status to Suspended. */
- void suspend(int delay = 0);
+ void suspend(Cycles delay = Cycles(0));
/** Set the status to Halted. */
- void halt(int delay = 0);
+ void halt(Cycles delay = Cycles(0));
/** Takes over execution of a thread from another CPU. */
void takeOverFrom(ThreadContext *old_context);
/** Registers statistics associated with this TC. */
void regStats(const std::string &name);
- /** Serializes state. */
- void serialize(std::ostream &os);
-
- /** Unserializes state. */
- void unserialize(Checkpoint *cp, const std::string §ion);
-
/** Returns this thread's ID number. */
int getThreadNum() { return thread->threadId(); }
FloatRegBits readFloatRegBits(int reg_idx);
+ CCReg readCCReg(int reg_idx);
+
uint64_t readRegOtherThread(int misc_reg, ThreadID tid);
/** Sets an integer register to a value. */
void setFloatRegBits(int reg_idx, FloatRegBits val);
+ void setCCReg(int reg_idx, CCReg val);
+
void setRegOtherThread(int misc_reg,
const MiscReg &val,
ThreadID tid);
void pcState(const TheISA::PCState &val)
{ cpu->pcState(val, thread->threadId()); }
+ /** Needs to be implemented for future CheckerCPU support.
+ * See O3CPU for examples on how to integrate Checker.
+ */
+ void pcStateNoRecord(const TheISA::PCState &val)
+ {}
+
Addr instAddr()
{ return cpu->instAddr(thread->threadId()); }
void setMiscReg(int misc_reg, const MiscReg &val);
int flattenIntIndex(int reg)
- { return cpu->isa[thread->threadId()].flattenIntIndex(reg); }
+ { return cpu->isa[thread->threadId()]->flattenIntIndex(reg); }
int flattenFloatIndex(int reg)
- { return cpu->isa[thread->threadId()].flattenFloatIndex(reg); }
+ { return cpu->isa[thread->threadId()]->flattenFloatIndex(reg); }
- void activateContext(int delay)
+ int flattenCCIndex(int reg)
+ { return cpu->isa[thread->threadId()]->flattenCCIndex(reg); }
+
+ int flattenMiscIndex(int reg)
+ { return cpu->isa[thread->threadId()]->flattenMiscIndex(reg); }
+
+ void activateContext(Cycles delay)
{ cpu->activateContext(thread->threadId(), delay); }
void deallocateContext()
* misspeculating, this is set as false. */
bool misspeculating() { return false; }
-#if !FULL_SYSTEM
/** Executes a syscall in SE mode. */
void syscall(int64_t callnum)
{ return cpu->syscall(callnum, thread->threadId()); }
-#endif
/** Reads the funcExeInst counter. */
Counter readFuncExeInst() { return thread->funcExeInst; }
void changeRegFileContext(unsigned param,
unsigned val)
{ panic("Not supported!"); }
+
+ uint64_t readIntRegFlat(int idx);
+ void setIntRegFlat(int idx, uint64_t val);
+
+ FloatReg readFloatRegFlat(int idx);
+ void setFloatRegFlat(int idx, FloatReg val);
+
+ FloatRegBits readFloatRegBitsFlat(int idx);
+ void setFloatRegBitsFlat(int idx, FloatRegBits val);
+
+ CCReg readCCRegFlat(int idx);
+ void setCCRegFlat(int idx, CCReg val);
};
#endif
projects / gem5.git / blobdiff