sim: Make the drain state a global typed enum

[gem5.git] / src / cpu / inteltrace.cc

diff --git a/src/cpu/inteltrace.cc b/src/cpu/inteltrace.cc
index afa51b517a70c6ad7b44c88256919b5d978ee83c..05bdc64d093f734652474117a7bd95eaf2ef27d8 100644 (file)
--- a/src/cpu/inteltrace.cc
+++ b/src/cpu/inteltrace.cc
@@ -33,10 +33,10 @@
 
 #include <iomanip>
 
+#include "config/the_isa.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/inteltrace.hh"
 #include "cpu/static_inst.hh"
-#include "params/IntelTrace.hh"
 
 using namespace std;
 using namespace TheISA;
@@ -48,7 +48,7 @@ Trace::IntelTraceRecord::dump()
 {
     ostream &outs = Trace::output();
     ccprintf(outs, "%7d ) ", when);
-    outs << "0x" << hex << PC << ":\t";
+    outs << "0x" << hex << pc.instAddr() << ":\t";
     if (staticInst->isLoad()) {
         ccprintf(outs, "<RD %#x>", addr);
     } else if (staticInst->isStore()) {
@@ -57,7 +57,7 @@ Trace::IntelTraceRecord::dump()
     outs << endl;
 }
 
-/* namespace Trace */ }
+} // namespace Trace
 
 ////////////////////////////////////////////////////////////////////////
 //
@@ -66,5 +66,5 @@ Trace::IntelTraceRecord::dump()
 Trace::IntelTrace *
 IntelTraceParams::create()
 {
-    return new Trace::IntelTrace(name);
-};
+    return new Trace::IntelTrace(this);
+}