cpu: re-organizes the branch predictor structure.

[gem5.git] / src / cpu / intr_control.cc

diff --git a/src/cpu/intr_control.cc b/src/cpu/intr_control.cc
index 3171a352fb8ebcb2dcf11ee3ba68662319a77dd7..8f3808889e69979fd5caecd9f3db8cadb39853d7 100644 (file)
--- a/src/cpu/intr_control.cc
+++ b/src/cpu/intr_control.cc
@@ -32,69 +32,39 @@
 #include <string>
 #include <vector>
 
+#include "base/trace.hh"
 #include "cpu/base.hh"
-#include "cpu/exec_context.hh"
 #include "cpu/intr_control.hh"
-#include "sim/builder.hh"
+#include "cpu/thread_context.hh"
+#include "debug/IntrControl.hh"
 #include "sim/sim_object.hh"
 
 using namespace std;
 
-IntrControl::IntrControl(const string &name, BaseCPU *c)
-    : SimObject(name), cpu(c)
+IntrControl::IntrControl(const Params *p)
+    : SimObject(p), sys(p->sys)
 {}
 
-/* @todo
- *Fix the cpu sim object parameter to be a system pointer
- *instead, to avoid some extra dereferencing
- */
-void
-IntrControl::post(int int_num, int index)
-{
-    std::vector<ExecContext *> &xcvec = cpu->system->execContexts;
-    BaseCPU *temp = xcvec[0]->getCpuPtr();
-    temp->post_interrupt(int_num, index);
-}
-
 void
 IntrControl::post(int cpu_id, int int_num, int index)
 {
-    std::vector<ExecContext *> &xcvec = cpu->system->execContexts;
-    BaseCPU *temp = xcvec[cpu_id]->getCpuPtr();
-    temp->post_interrupt(int_num, index);
-}
-
-void
-IntrControl::clear(int int_num, int index)
-{
-    std::vector<ExecContext *> &xcvec = cpu->system->execContexts;
-    BaseCPU *temp = xcvec[0]->getCpuPtr();
-    temp->clear_interrupt(int_num, index);
+    DPRINTF(IntrControl, "post  %d:%d (cpu %d)\n", int_num, index, cpu_id);
+    std::vector<ThreadContext *> &tcvec = sys->threadContexts;
+    BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr();
+    cpu->postInterrupt(int_num, index);
 }
 
 void
 IntrControl::clear(int cpu_id, int int_num, int index)
 {
-    std::vector<ExecContext *> &xcvec = cpu->system->execContexts;
-    BaseCPU *temp = xcvec[cpu_id]->getCpuPtr();
-    temp->clear_interrupt(int_num, index);
+    DPRINTF(IntrControl, "clear %d:%d (cpu %d)\n", int_num, index, cpu_id);
+    std::vector<ThreadContext *> &tcvec = sys->threadContexts;
+    BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr();
+    cpu->clearInterrupt(int_num, index);
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(IntrControl)
-
-    SimObjectParam<BaseCPU *> cpu;
-
-END_DECLARE_SIM_OBJECT_PARAMS(IntrControl)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(IntrControl)
-
-    INIT_PARAM(cpu, "the cpu")
-
-END_INIT_SIM_OBJECT_PARAMS(IntrControl)
-
-CREATE_SIM_OBJECT(IntrControl)
+IntrControl *
+IntrControlParams::create()
 {
-    return new IntrControl(getInstanceName(), cpu);
+    return new IntrControl(this);
 }
-
-REGISTER_SIM_OBJECT("IntrControl", IntrControl)