#include "base/misc.hh"
#include "base/statistics.hh"
#include "cpu/memtest/memtest.hh"
-//#include "cpu/simple_thread.hh"
-//#include "mem/cache/base_cache.hh"
#include "mem/mem_object.hh"
#include "mem/port.hh"
#include "mem/packet.hh"
-//#include "mem/physical.hh"
#include "mem/request.hh"
-#include "params/MemTest.hh"
#include "sim/sim_events.hh"
#include "sim/stats.hh"
bool
MemTest::CpuPort::recvTiming(PacketPtr pkt)
{
- memtest->completeRequest(pkt);
+ if (pkt->isResponse()) {
+ memtest->completeRequest(pkt);
+ } else {
+ // must be snoop upcall
+ assert(pkt->isRequest());
+ assert(pkt->getDest() == Packet::Broadcast);
+ }
return true;
}
Tick
MemTest::CpuPort::recvAtomic(PacketPtr pkt)
{
- panic("MemTest doesn't expect recvAtomic callback!");
+ // must be snoop upcall
+ assert(pkt->isRequest());
+ assert(pkt->getDest() == Packet::Broadcast);
return curTick;
}
MemTest::sendPkt(PacketPtr pkt) {
if (atomic) {
cachePort.sendAtomic(pkt);
- pkt->makeAtomicResponse();
completeRequest(pkt);
}
else if (!cachePort.sendTiming(pkt)) {
}
-MemTest::MemTest(const string &name,
-// MemInterface *_cache_interface,
-// PhysicalMemory *main_mem,
-// PhysicalMemory *check_mem,
- unsigned _memorySize,
- unsigned _percentReads,
- unsigned _percentFunctional,
- unsigned _percentUncacheable,
- unsigned _progressInterval,
- unsigned _percentSourceUnaligned,
- unsigned _percentDestUnaligned,
- Addr _traceAddr,
- Counter _max_loads,
- bool _atomic)
- : MemObject(name),
+MemTest::MemTest(const Params *p)
+ : MemObject(p),
tickEvent(this),
cachePort("test", this),
funcPort("functional", this),
retryPkt(NULL),
// mainMem(main_mem),
// checkMem(check_mem),
- size(_memorySize),
- percentReads(_percentReads),
- percentFunctional(_percentFunctional),
- percentUncacheable(_percentUncacheable),
- progressInterval(_progressInterval),
- nextProgressMessage(_progressInterval),
- percentSourceUnaligned(_percentSourceUnaligned),
- percentDestUnaligned(percentDestUnaligned),
- maxLoads(_max_loads),
- atomic(_atomic)
+ size(p->memory_size),
+ percentReads(p->percent_reads),
+ percentFunctional(p->percent_functional),
+ percentUncacheable(p->percent_uncacheable),
+ progressInterval(p->progress_interval),
+ nextProgressMessage(p->progress_interval),
+ percentSourceUnaligned(p->percent_source_unaligned),
+ percentDestUnaligned(p->percent_dest_unaligned),
+ maxLoads(p->max_loads),
+ atomic(p->atomic)
{
vector<string> cmd;
cmd.push_back("/bin/ls");
funcPort.snoopRangeSent = true;
// Needs to be masked off once we know the block size.
- traceBlockAddr = _traceAddr;
+ traceBlockAddr = p->trace_addr;
baseAddr1 = 0x100000;
baseAddr2 = 0x400000;
uncacheAddr = 0x800000;
// set up counters
noResponseCycles = 0;
numReads = 0;
- tickEvent.schedule(0);
+ schedule(tickEvent, 0);
id = TESTER_ALLOCATOR++;
- if (TESTER_ALLOCATOR > 8)
- panic("False sharing memtester only allows up to 8 testers");
accessRetry = false;
}
// memory should be 0; no need to initialize them.
}
-static void
-printData(ostream &os, uint8_t *data, int nbytes)
-{
- os << hex << setfill('0');
- // assume little-endian: print bytes from highest address to lowest
- for (uint8_t *dp = data + nbytes - 1; dp >= data; --dp) {
- os << setw(2) << (unsigned)*dp;
- }
- os << dec;
-}
void
MemTest::completeRequest(PacketPtr pkt)
{
+ Request *req = pkt->req;
+
+ DPRINTF(MemTest, "completing %s at address %x (blk %x)\n",
+ pkt->isWrite() ? "write" : "read",
+ req->getPaddr(), blockAddr(req->getPaddr()));
+
MemTestSenderState *state =
dynamic_cast<MemTestSenderState *>(pkt->senderState);
uint8_t *data = state->data;
uint8_t *pkt_data = pkt->getPtr<uint8_t>();
- Request *req = pkt->req;
//Remove the address from the list of outstanding
- std::set<unsigned>::iterator removeAddr = outstandingAddrs.find(req->getPaddr());
+ std::set<unsigned>::iterator removeAddr =
+ outstandingAddrs.find(req->getPaddr());
assert(removeAddr != outstandingAddrs.end());
outstandingAddrs.erase(removeAddr);
- switch (pkt->cmd.toInt()) {
- case MemCmd::ReadResp:
+ assert(pkt->isResponse());
+ if (pkt->isRead()) {
if (memcmp(pkt_data, data, pkt->getSize()) != 0) {
- cerr << name() << ": on read of 0x" << hex << req->getPaddr()
- << " (0x" << hex << blockAddr(req->getPaddr()) << ")"
- << "@ cycle " << dec << curTick
- << ", cache returns 0x";
- printData(cerr, pkt_data, pkt->getSize());
- cerr << ", expected 0x";
- printData(cerr, data, pkt->getSize());
- cerr << endl;
- fatal("");
+ panic("%s: read of %x (blk %x) @ cycle %d "
+ "returns %x, expected %x\n", name(),
+ req->getPaddr(), blockAddr(req->getPaddr()), curTick,
+ *pkt_data, *data);
}
numReads++;
nextProgressMessage += progressInterval;
}
- if (numReads >= maxLoads)
- exitSimLoop("Maximum number of loads reached!");
- break;
-
- case MemCmd::WriteResp:
+ if (maxLoads != 0 && numReads >= maxLoads)
+ exitSimLoop("maximum number of loads reached");
+ } else {
+ assert(pkt->isWrite());
numWritesStat++;
- break;
-/*
- case Copy:
- //Also remove dest from outstanding list
- removeAddr = outstandingAddrs.find(req->dest);
- assert(removeAddr != outstandingAddrs.end());
- outstandingAddrs.erase(removeAddr);
- numCopiesStat++;
- break;
-*/
- default:
- panic("invalid command %s (%d)", pkt->cmdString(), pkt->cmd.toInt());
- }
-
- if (blockAddr(req->getPaddr()) == traceBlockAddr) {
- cerr << name() << ": completed "
- << (pkt->isWrite() ? "write" : "read")
- << " access of "
- << dec << pkt->getSize() << " bytes at address 0x"
- << hex << req->getPaddr()
- << " (0x" << hex << blockAddr(req->getPaddr()) << ")"
- << ", value = 0x";
- printData(cerr, pkt_data, pkt->getSize());
- cerr << " @ cycle " << dec << curTick;
-
- cerr << endl;
}
noResponseCycles = 0;
MemTest::tick()
{
if (!tickEvent.scheduled())
- tickEvent.schedule(curTick + cycles(1));
+ schedule(tickEvent, curTick + ticks(1));
if (++noResponseCycles >= 500000) {
cerr << name() << ": deadlocked at cycle " << curTick << endl;
unsigned base = random() % 2;
uint64_t data = random();
unsigned access_size = random() % 4;
- unsigned cacheable = random() % 100;
+ bool uncacheable = (random() % 100) < percentUncacheable;
//If we aren't doing copies, use id as offset, and do a false sharing
//mem tester
//We can eliminate the lower bits of the offset, and then use the id
//to offset within the blks
- offset &= ~63; //Not the low order bits
+ offset = blockAddr(offset);
offset += id;
access_size = 0;
Request *req = new Request();
- uint32_t flags = 0;
+ Request::Flags flags;
Addr paddr;
- if (cacheable < percentUncacheable) {
- flags |= UNCACHEABLE;
+ if (uncacheable) {
+ flags.set(Request::UNCACHEABLE);
paddr = uncacheAddr + offset;
} else {
paddr = ((base) ? baseAddr1 : baseAddr2) + offset;
}
- bool probe = (random() % 100 < percentFunctional) && !(flags & UNCACHEABLE);
- //bool probe = false;
+ bool probe = (random() % 100 < percentFunctional) && !uncacheable;
paddr &= ~((1 << access_size) - 1);
req->setPhys(paddr, 1 << access_size, flags);
if (cmd < percentReads) {
// read
- //For now we only allow one outstanding request per addreess per tester
- //This means we assume CPU does write forwarding to reads that alias something
- //in the cpu store buffer.
+ // For now we only allow one outstanding request per address
+ // per tester This means we assume CPU does write forwarding
+ // to reads that alias something in the cpu store buffer.
if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
delete [] result;
delete req;
return;
}
- else outstandingAddrs.insert(paddr);
+
+ outstandingAddrs.insert(paddr);
// ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin
funcPort.readBlob(req->getPaddr(), result, req->getSize());
- if (blockAddr(paddr) == traceBlockAddr) {
- cerr << name()
- << ": initiating read "
- << ((probe) ? "probe of " : "access of ")
- << dec << req->getSize() << " bytes from addr 0x"
- << hex << paddr
- << " (0x" << hex << blockAddr(paddr) << ")"
- << " at cycle "
- << dec << curTick << endl;
- }
+ DPRINTF(MemTest,
+ "initiating read at address %x (blk %x) expecting %x\n",
+ req->getPaddr(), blockAddr(req->getPaddr()), *result);
PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
+ pkt->setSrc(0);
pkt->dataDynamicArray(new uint8_t[req->getSize()]);
MemTestSenderState *state = new MemTestSenderState(result);
pkt->senderState = state;
if (probe) {
cachePort.sendFunctional(pkt);
- pkt->makeAtomicResponse();
completeRequest(pkt);
} else {
-// req->completionEvent = new MemCompleteEvent(req, result, this);
sendPkt(pkt);
}
} else {
// write
- //For now we only allow one outstanding request per addreess per tester
- //This means we assume CPU does write forwarding to reads that alias something
- //in the cpu store buffer.
+ // For now we only allow one outstanding request per addreess
+ // per tester. This means we assume CPU does write forwarding
+ // to reads that alias something in the cpu store buffer.
if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
delete [] result;
delete req;
return;
}
- else outstandingAddrs.insert(paddr);
+ outstandingAddrs.insert(paddr);
+
+ DPRINTF(MemTest, "initiating write at address %x (blk %x) value %x\n",
+ req->getPaddr(), blockAddr(req->getPaddr()), data & 0xff);
-/*
- if (blockAddr(req->getPaddr()) == traceBlockAddr) {
- cerr << name() << ": initiating write "
- << ((probe)?"probe of ":"access of ")
- << dec << req->getSize() << " bytes (value = 0x";
- printData(cerr, data_pkt->getPtr(), req->getSize());
- cerr << ") to addr 0x"
- << hex << req->getPaddr()
- << " (0x" << hex << blockAddr(req->getPaddr()) << ")"
- << " at cycle "
- << dec << curTick << endl;
- }
-*/
PacketPtr pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
+ pkt->setSrc(0);
uint8_t *pkt_data = new uint8_t[req->getSize()];
pkt->dataDynamicArray(pkt_data);
memcpy(pkt_data, &data, req->getSize());
if (probe) {
cachePort.sendFunctional(pkt);
- pkt->makeAtomicResponse();
completeRequest(pkt);
} else {
-// req->completionEvent = new MemCompleteEvent(req, NULL, this);
sendPkt(pkt);
}
}
-/* else {
- // copy
- unsigned source_align = random() % 100;
- unsigned dest_align = random() % 100;
- unsigned offset2 = random() % size;
-
- Addr source = ((base) ? baseAddr1 : baseAddr2) + offset;
- Addr dest = ((base) ? baseAddr2 : baseAddr1) + offset2;
- if (outstandingAddrs.find(source) != outstandingAddrs.end()) return;
- else outstandingAddrs.insert(source);
- if (outstandingAddrs.find(dest) != outstandingAddrs.end()) return;
- else outstandingAddrs.insert(dest);
-
- if (source_align >= percentSourceUnaligned) {
- source = blockAddr(source);
- }
- if (dest_align >= percentDestUnaligned) {
- dest = blockAddr(dest);
- }
- req->cmd = Copy;
- req->flags &= ~UNCACHEABLE;
- req->paddr = source;
- req->dest = dest;
- delete [] req->data;
- req->data = new uint8_t[blockSize];
- req->size = blockSize;
- if (source == traceBlockAddr || dest == traceBlockAddr) {
- cerr << name()
- << ": initiating copy of "
- << dec << req->size << " bytes from addr 0x"
- << hex << source
- << " (0x" << hex << blockAddr(source) << ")"
- << " to addr 0x"
- << hex << dest
- << " (0x" << hex << blockAddr(dest) << ")"
- << " at cycle "
- << dec << curTick << endl;
- }*
- cacheInterface->access(req);
- uint8_t result[blockSize];
- checkMem->access(Read, source, &result, blockSize);
- checkMem->access(Write, dest, &result, blockSize);
- }
-*/
}
void
}
}
+
+void
+MemTest::printAddr(Addr a)
+{
+ cachePort.printAddr(a);
+}
+
+
MemTest *
MemTestParams::create()
{
- return new MemTest(name,
-#if 0
- cache->getInterface(), main_mem, check_mem,
-#endif
- memory_size, percent_reads, percent_functional,
- percent_uncacheable, progress_interval,
- percent_source_unaligned, percent_dest_unaligned,
- trace_addr, max_loads, atomic);
+ return new MemTest(this);
}
projects / gem5.git / blobdiff