#include "base/misc.hh"
#include "base/statistics.hh"
#include "cpu/memtest/memtest.hh"
-//#include "cpu/simple_thread.hh"
-//#include "mem/cache/base_cache.hh"
#include "mem/mem_object.hh"
#include "mem/port.hh"
#include "mem/packet.hh"
-//#include "mem/physical.hh"
#include "mem/request.hh"
-#include "sim/builder.hh"
#include "sim/sim_events.hh"
#include "sim/stats.hh"
}
-MemTest::MemTest(const string &name,
-// MemInterface *_cache_interface,
-// PhysicalMemory *main_mem,
-// PhysicalMemory *check_mem,
- unsigned _memorySize,
- unsigned _percentReads,
- unsigned _percentFunctional,
- unsigned _percentUncacheable,
- unsigned _progressInterval,
- unsigned _percentSourceUnaligned,
- unsigned _percentDestUnaligned,
- Addr _traceAddr,
- Counter _max_loads,
- bool _atomic)
- : MemObject(name),
+MemTest::MemTest(const Params *p)
+ : MemObject(p),
tickEvent(this),
cachePort("test", this),
funcPort("functional", this),
retryPkt(NULL),
// mainMem(main_mem),
// checkMem(check_mem),
- size(_memorySize),
- percentReads(_percentReads),
- percentFunctional(_percentFunctional),
- percentUncacheable(_percentUncacheable),
- progressInterval(_progressInterval),
- nextProgressMessage(_progressInterval),
- percentSourceUnaligned(_percentSourceUnaligned),
- percentDestUnaligned(percentDestUnaligned),
- maxLoads(_max_loads),
- atomic(_atomic)
+ size(p->memory_size),
+ percentReads(p->percent_reads),
+ percentFunctional(p->percent_functional),
+ percentUncacheable(p->percent_uncacheable),
+ progressInterval(p->progress_interval),
+ nextProgressMessage(p->progress_interval),
+ percentSourceUnaligned(p->percent_source_unaligned),
+ percentDestUnaligned(p->percent_dest_unaligned),
+ maxLoads(p->max_loads),
+ atomic(p->atomic)
{
vector<string> cmd;
cmd.push_back("/bin/ls");
funcPort.snoopRangeSent = true;
// Needs to be masked off once we know the block size.
- traceBlockAddr = _traceAddr;
+ traceBlockAddr = p->trace_addr;
baseAddr1 = 0x100000;
baseAddr2 = 0x400000;
uncacheAddr = 0x800000;
// set up counters
noResponseCycles = 0;
numReads = 0;
- tickEvent.schedule(0);
+ schedule(tickEvent, 0);
id = TESTER_ALLOCATOR++;
assert(removeAddr != outstandingAddrs.end());
outstandingAddrs.erase(removeAddr);
- switch (pkt->cmd.toInt()) {
- case MemCmd::ReadResp:
+ assert(pkt->isResponse());
+ if (pkt->isRead()) {
if (memcmp(pkt_data, data, pkt->getSize()) != 0) {
panic("%s: read of %x (blk %x) @ cycle %d "
"returns %x, expected %x\n", name(),
if (maxLoads != 0 && numReads >= maxLoads)
exitSimLoop("maximum number of loads reached");
- break;
-
- case MemCmd::WriteResp:
+ } else {
+ assert(pkt->isWrite());
numWritesStat++;
- break;
-
- default:
- panic("invalid command %s (%d)", pkt->cmdString(), pkt->cmd.toInt());
}
noResponseCycles = 0;
MemTest::tick()
{
if (!tickEvent.scheduled())
- tickEvent.schedule(curTick + cycles(1));
+ schedule(tickEvent, curTick + ticks(1));
if (++noResponseCycles >= 500000) {
cerr << name() << ": deadlocked at cycle " << curTick << endl;
unsigned base = random() % 2;
uint64_t data = random();
unsigned access_size = random() % 4;
- unsigned cacheable = random() % 100;
+ bool uncacheable = (random() % 100) < percentUncacheable;
//If we aren't doing copies, use id as offset, and do a false sharing
//mem tester
access_size = 0;
Request *req = new Request();
- uint32_t flags = 0;
+ Request::Flags flags;
Addr paddr;
- if (cacheable < percentUncacheable) {
- flags |= UNCACHEABLE;
+ if (uncacheable) {
+ flags.set(Request::UNCACHEABLE);
paddr = uncacheAddr + offset;
} else {
paddr = ((base) ? baseAddr1 : baseAddr2) + offset;
}
- bool probe = (random() % 100 < percentFunctional) && !(flags & UNCACHEABLE);
- //bool probe = false;
+ bool probe = (random() % 100 < percentFunctional) && !uncacheable;
paddr &= ~((1 << access_size) - 1);
req->setPhys(paddr, 1 << access_size, flags);
if (probe) {
cachePort.sendFunctional(pkt);
- pkt->makeAtomicResponse();
completeRequest(pkt);
} else {
sendPkt(pkt);
if (probe) {
cachePort.sendFunctional(pkt);
- pkt->makeAtomicResponse();
completeRequest(pkt);
} else {
sendPkt(pkt);
}
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(MemTest)
-
-// SimObjectParam<BaseCache *> cache;
-// SimObjectParam<PhysicalMemory *> main_mem;
-// SimObjectParam<PhysicalMemory *> check_mem;
- Param<unsigned> memory_size;
- Param<unsigned> percent_reads;
- Param<unsigned> percent_functional;
- Param<unsigned> percent_uncacheable;
- Param<unsigned> progress_interval;
- Param<unsigned> percent_source_unaligned;
- Param<unsigned> percent_dest_unaligned;
- Param<Addr> trace_addr;
- Param<Counter> max_loads;
- Param<bool> atomic;
-
-END_DECLARE_SIM_OBJECT_PARAMS(MemTest)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(MemTest)
-
-// INIT_PARAM(cache, "L1 cache"),
-// INIT_PARAM(main_mem, "hierarchical memory"),
-// INIT_PARAM(check_mem, "check memory"),
- INIT_PARAM(memory_size, "memory size"),
- INIT_PARAM(percent_reads, "target read percentage"),
- INIT_PARAM(percent_functional, "percentage of access that are functional"),
- INIT_PARAM(percent_uncacheable, "target uncacheable percentage"),
- INIT_PARAM(progress_interval, "progress report interval (in accesses)"),
- INIT_PARAM(percent_source_unaligned,
- "percent of copy source address that are unaligned"),
- INIT_PARAM(percent_dest_unaligned,
- "percent of copy dest address that are unaligned"),
- INIT_PARAM(trace_addr, "address to trace"),
- INIT_PARAM(max_loads, "terminate when we have reached this load count"),
- INIT_PARAM(atomic, "Is the tester testing atomic mode (or timing)")
-
-END_INIT_SIM_OBJECT_PARAMS(MemTest)
-
-
-CREATE_SIM_OBJECT(MemTest)
+
+void
+MemTest::printAddr(Addr a)
{
- return new MemTest(getInstanceName(), /*cache->getInterface(),*/ /*main_mem,*/
- /*check_mem,*/ memory_size, percent_reads, percent_functional,
- percent_uncacheable, progress_interval,
- percent_source_unaligned, percent_dest_unaligned,
- trace_addr, max_loads, atomic);
+ cachePort.printAddr(a);
}
-REGISTER_SIM_OBJECT("MemTest", MemTest)
+
+MemTest *
+MemTestParams::create()
+{
+ return new MemTest(this);
+}
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