#include <set>
#include "base/statistics.hh"
-//#include "mem/functional/functional.hh"
-//#include "mem/mem_interface.hh"
+#include "base/fast_alloc.hh"
+#include "params/MemTest.hh"
#include "sim/eventq.hh"
#include "sim/sim_exit.hh"
#include "sim/sim_object.hh"
class MemTest : public MemObject
{
public:
-
- MemTest(const std::string &name,
-// MemInterface *_cache_interface,
-// PhysicalMemory *main_mem,
-// PhysicalMemory *check_mem,
- unsigned _memorySize,
- unsigned _percentReads,
- unsigned _percentFunctional,
- unsigned _percentUncacheable,
- unsigned _progressInterval,
- unsigned _percentSourceUnaligned,
- unsigned _percentDestUnaligned,
- Addr _traceAddr,
- Counter _max_loads,
- bool _atomic);
+ typedef MemTestParams Params;
+ MemTest(const Params *p);
virtual void init();
// register statistics
virtual void regStats();
- inline Tick cycles(int numCycles) const { return numCycles; }
+ inline Tick ticks(int numCycles) const { return numCycles; }
// main simulation loop (one cycle)
void tick();
virtual Port *getPort(const std::string &if_name, int idx = -1);
+ /**
+ * Print state of address in memory system via PrintReq (for
+ * debugging).
+ */
+ void printAddr(Addr a);
+
protected:
class TickEvent : public Event
{
private:
MemTest *cpu;
+
public:
- TickEvent(MemTest *c)
- : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) {}
- void process() {cpu->tick();}
- virtual const char *description() { return "tick event"; }
+ TickEvent(MemTest *c) : Event(CPU_Tick_Pri), cpu(c) {}
+ void process() { cpu->tick(); }
+ virtual const char *description() const { return "MemTest tick"; }
};
TickEvent tickEvent;
+
class CpuPort : public Port
{
-
MemTest *memtest;
public:
: Port(_name, _memtest), memtest(_memtest)
{ }
+ bool snoopRangeSent;
+
protected:
virtual bool recvTiming(PacketPtr pkt);
virtual void recvRetry();
virtual void getDeviceAddressRanges(AddrRangeList &resp,
- AddrRangeList &snoop)
- { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,-1)); }
+ bool &snoop)
+ { resp.clear(); snoop = false; }
};
CpuPort cachePort;
CpuPort funcPort;
- class MemTestSenderState : public Packet::SenderState
+ bool snoopRangeSent;
+
+ class MemTestSenderState : public Packet::SenderState, public FastAlloc
{
public:
/** Constructor. */
uint8_t *data;
};
-// Request *dataReq;
PacketPtr retryPkt;
-// MemInterface *cacheInterface;
-// PhysicalMemory *mainMem;
-// PhysicalMemory *checkMem;
-// SimpleThread *thread;
bool accessRetry;
+
+ //
+ // The dmaOustanding flag enforces only one dma at a time
+ //
+ bool dmaOutstanding;
- unsigned size; // size of testing memory region
+ unsigned size; // size of testing memory region
- unsigned percentReads; // target percentage of read accesses
- unsigned percentFunctional; // target percentage of functional accesses
+ unsigned percentReads; // target percentage of read accesses
+ unsigned percentFunctional; // target percentage of functional accesses
unsigned percentUncacheable;
+ bool issueDmas;
+
int id;
std::set<unsigned> outstandingAddrs;
Addr traceBlockAddr;
- Addr baseAddr1; // fix this to option
- Addr baseAddr2; // fix this to option
+ Addr baseAddr1; // fix this to option
+ Addr baseAddr2; // fix this to option
Addr uncacheAddr;
- unsigned progressInterval; // frequency of progress reports
- Tick nextProgressMessage; // access # for next progress report
+ unsigned progressInterval; // frequency of progress reports
+ Tick nextProgressMessage; // access # for next progress report
unsigned percentSourceUnaligned;
unsigned percentDestUnaligned;
bool atomic;
- Stats::Scalar<> numReadsStat;
- Stats::Scalar<> numWritesStat;
- Stats::Scalar<> numCopiesStat;
+ Stats::Scalar numReadsStat;
+ Stats::Scalar numWritesStat;
+ Stats::Scalar numCopiesStat;
// called by MemCompleteEvent::process()
void completeRequest(PacketPtr pkt);