X86: Add a .serializing directive that makes a macroop serializing.

[gem5.git] / src / cpu / memtest / memtest.hh

diff --git a/src/cpu/memtest/memtest.hh b/src/cpu/memtest/memtest.hh
index 42fb235db43a6ada9a9d4b4343b029244c3b0078..bb71da355dc9b750350df61965119ac4ea6173c0 100644 (file)
--- a/src/cpu/memtest/memtest.hh
+++ b/src/cpu/memtest/memtest.hh
@@ -35,65 +35,117 @@
 #include <set>
 
 #include "base/statistics.hh"
-#include "mem/functional/functional.hh"
-#include "mem/mem_interface.hh"
+#include "base/fast_alloc.hh"
+#include "params/MemTest.hh"
 #include "sim/eventq.hh"
 #include "sim/sim_exit.hh"
 #include "sim/sim_object.hh"
 #include "sim/stats.hh"
+#include "mem/mem_object.hh"
+#include "mem/port.hh"
 
-class ThreadContext;
-class MemTest : public SimObject
+class Packet;
+class MemTest : public MemObject
 {
   public:
+    typedef MemTestParams Params;
+    MemTest(const Params *p);
 
-    MemTest(const std::string &name,
-            MemInterface *_cache_interface,
-            FunctionalMemory *main_mem,
-            FunctionalMemory *check_mem,
-            unsigned _memorySize,
-            unsigned _percentReads,
-            unsigned _percentCopies,
-            unsigned _percentUncacheable,
-            unsigned _progressInterval,
-            unsigned _percentSourceUnaligned,
-            unsigned _percentDestUnaligned,
-            Addr _traceAddr,
-            Counter _max_loads);
+    virtual void init();
 
     // register statistics
     virtual void regStats();
 
-    inline Tick cycles(int numCycles) const { return numCycles; }
+    inline Tick ticks(int numCycles) const { return numCycles; }
 
     // main simulation loop (one cycle)
     void tick();
 
+    virtual Port *getPort(const std::string &if_name, int idx = -1);
+
+    /**
+     * Print state of address in memory system via PrintReq (for
+     * debugging).
+     */
+    void printAddr(Addr a);
+
   protected:
     class TickEvent : public Event
     {
       private:
         MemTest *cpu;
+
       public:
-        TickEvent(MemTest *c)
-            : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) {}
-        void process() {cpu->tick();}
-        virtual const char *description() { return "tick event"; }
+        TickEvent(MemTest *c) : Event(CPU_Tick_Pri), cpu(c) {}
+        void process() { cpu->tick(); }
+        virtual const char *description() const { return "MemTest tick"; }
     };
 
     TickEvent tickEvent;
 
-    MemInterface *cacheInterface;
-    FunctionalMemory *mainMem;
-    FunctionalMemory *checkMem;
-    SimpleThread *thread;
+    class CpuPort : public Port
+    {
+        MemTest *memtest;
+
+      public:
+
+        CpuPort(const std::string &_name, MemTest *_memtest)
+            : Port(_name, _memtest), memtest(_memtest)
+        { }
+
+        bool snoopRangeSent;
+
+      protected:
+
+        virtual bool recvTiming(PacketPtr pkt);
 
-    unsigned size;             // size of testing memory region
+        virtual Tick recvAtomic(PacketPtr pkt);
 
-    unsigned percentReads;     // target percentage of read accesses
-    unsigned percentCopies;    // target percentage of copy accesses
+        virtual void recvFunctional(PacketPtr pkt);
+
+        virtual void recvStatusChange(Status status);
+
+        virtual void recvRetry();
+
+        virtual void getDeviceAddressRanges(AddrRangeList &resp,
+                                            bool &snoop)
+        { resp.clear(); snoop = false; }
+    };
+
+    CpuPort cachePort;
+    CpuPort funcPort;
+
+    bool snoopRangeSent;
+
+    class MemTestSenderState : public Packet::SenderState, public FastAlloc
+    {
+      public:
+        /** Constructor. */
+        MemTestSenderState(uint8_t *_data)
+            : data(_data)
+        { }
+
+        // Hold onto data pointer
+        uint8_t *data;
+    };
+
+    PacketPtr retryPkt;
+
+    bool accessRetry;
+    
+    //
+    // The dmaOustanding flag enforces only one dma at a time
+    //
+    bool dmaOutstanding;
+
+    unsigned size;              // size of testing memory region
+
+    unsigned percentReads;      // target percentage of read accesses
+    unsigned percentFunctional; // target percentage of functional accesses
     unsigned percentUncacheable;
 
+    bool issueDmas;
+
     int id;
 
     std::set<unsigned> outstandingAddrs;
@@ -109,12 +161,12 @@ class MemTest : public SimObject
 
     Addr traceBlockAddr;
 
-    Addr baseAddr1;            // fix this to option
-    Addr baseAddr2;            // fix this to option
+    Addr baseAddr1;             // fix this to option
+    Addr baseAddr2;             // fix this to option
     Addr uncacheAddr;
 
-    unsigned progressInterval; // frequency of progress reports
-    Tick nextProgressMessage;  // access # for next progress report
+    unsigned progressInterval;  // frequency of progress reports
+    Tick nextProgressMessage;   // access # for next progress report
 
     unsigned percentSourceUnaligned;
     unsigned percentDestUnaligned;
@@ -123,34 +175,21 @@ class MemTest : public SimObject
 
     uint64_t numReads;
     uint64_t maxLoads;
-    Stats::Scalar<> numReadsStat;
-    Stats::Scalar<> numWritesStat;
-    Stats::Scalar<> numCopiesStat;
-
-    // called by MemCompleteEvent::process()
-    void completeRequest(MemReqPtr &req, uint8_t *data);
 
-    friend class MemCompleteEvent;
-};
+    bool atomic;
 
+    Stats::Scalar numReadsStat;
+    Stats::Scalar numWritesStat;
+    Stats::Scalar numCopiesStat;
 
-class MemCompleteEvent : public Event
-{
-    MemReqPtr req;
-    uint8_t *data;
-    MemTest *tester;
-
-  public:
+    // called by MemCompleteEvent::process()
+    void completeRequest(PacketPtr pkt);
 
-    MemCompleteEvent(MemReqPtr &_req, uint8_t *_data, MemTest *_tester)
-        : Event(&mainEventQueue),
-          req(_req), data(_data), tester(_tester)
-    {
-    }
+    void sendPkt(PacketPtr pkt);
 
-    void process();
+    void doRetry();
 
-    virtual const char *description();
+    friend class MemCompleteEvent;
 };
 
 #endif // __CPU_MEMTEST_MEMTEST_HH__