cpu: Turn the stage 2 ARM MMUs from params to children.

[gem5.git] / src / cpu / minor / fetch1.cc

diff --git a/src/cpu/minor/fetch1.cc b/src/cpu/minor/fetch1.cc
index 0620fee1eb7021bf6e47b582f7437476a03fee9c..465372a08b8bc69a65afe4294ecb87aa47d90dae 100644 (file)
--- a/src/cpu/minor/fetch1.cc
+++ b/src/cpu/minor/fetch1.cc
@@ -168,8 +168,8 @@ Fetch1::fetchLine(ThreadID tid)
         "%s addr: 0x%x pc: %s line_offset: %d request_size: %d\n",
         request_id, aligned_pc, thread.pc, line_offset, request_size);
 
-    request->request.setContext(cpu.threads[tid]->getTC()->contextId());
-    request->request.setVirt(0 /* asid */,
+    request->request->setContext(cpu.threads[tid]->getTC()->contextId());
+    request->request->setVirt(0 /* asid */,
         aligned_pc, request_size, Request::INST_FETCH, cpu.instMasterId(),
         /* I've no idea why we need the PC, but give it */
         thread.pc.instAddr());
@@ -187,7 +187,7 @@ Fetch1::fetchLine(ThreadID tid)
      *  through finish/markDelayed on this request as it bears
      *  the Translation interface */
     cpu.threads[request->id.threadId]->itb->translateTiming(
-        &request->request,
+        request->request,
         cpu.getContext(request->id.threadId),
         request, BaseTLB::Execute);
 
@@ -228,7 +228,7 @@ void
 Fetch1::FetchRequest::makePacket()
 {
     /* Make the necessary packet for a memory transaction */
-    packet = new Packet(&request, MemCmd::ReadReq);
+    packet = new Packet(request, MemCmd::ReadReq);
     packet->allocate();
 
     /* This FetchRequest becomes SenderState to allow the response to be
@@ -237,7 +237,7 @@ Fetch1::FetchRequest::makePacket()
 }
 
 void
-Fetch1::FetchRequest::finish(const Fault &fault_, RequestPtr request_,
+Fetch1::FetchRequest::finish(const Fault &fault_, const RequestPtr &request_,
                              ThreadContext *tc, BaseTLB::Mode mode)
 {
     fault = fault_;
@@ -258,8 +258,9 @@ Fetch1::handleTLBResponse(FetchRequestPtr response)
         DPRINTF(Fetch, "Fault in address ITLB translation: %s, "
             "paddr: 0x%x, vaddr: 0x%x\n",
             response->fault->name(),
-            (response->request.hasPaddr() ? response->request.getPaddr() : 0),
-            response->request.getVaddr());
+            (response->request->hasPaddr() ?
+                response->request->getPaddr() : 0),
+            response->request->getVaddr());
 
         if (DTRACE(MinorTrace))
             minorTraceResponseLine(name(), response);
@@ -397,18 +398,18 @@ void
 Fetch1::minorTraceResponseLine(const std::string &name,
     Fetch1::FetchRequestPtr response) const
 {
-    Request &request M5_VAR_USED = response->request;
+    const RequestPtr &request M5_VAR_USED = response->request;
 
     if (response->packet && response->packet->isError()) {
         MINORLINE(this, "id=F;%s vaddr=0x%x fault=\"error packet\"\n",
-            response->id, request.getVaddr());
+            response->id, request->getVaddr());
     } else if (response->fault != NoFault) {
         MINORLINE(this, "id=F;%s vaddr=0x%x fault=\"%s\"\n",
-            response->id, request.getVaddr(), response->fault->name());
+            response->id, request->getVaddr(), response->fault->name());
     } else {
         MINORLINE(this, "id=%s size=%d vaddr=0x%x paddr=0x%x\n",
-            response->id, request.getSize(),
-            request.getVaddr(), request.getPaddr());
+            response->id, request->getSize(),
+            request->getVaddr(), request->getPaddr());
     }
 }
 
@@ -550,7 +551,7 @@ Fetch1::processResponse(Fetch1::FetchRequestPtr response,
     line.pc = response->pc;
     /* Set the lineBase, which is a sizeof(MachInst) aligned address <=
      *  pc.instAddr() */
-    line.lineBaseAddr = response->request.getVaddr();
+    line.lineBaseAddr = response->request->getVaddr();
 
     if (response->fault != NoFault) {
         /* Stop fetching if there was a fault */