Merge ktlim@zamp:/z/ktlim2/clean/m5-o3

[gem5.git] / src / cpu / o3 / alpha_dyn_inst.hh

diff --git a/src/cpu/o3/alpha_dyn_inst.hh b/src/cpu/o3/alpha_dyn_inst.hh
index af28588021acdaaa86c28460f3c8cac058565a6d..143ffe7e4f3d28b5e651146d58f91d1077a07b14 100644 (file)
--- a/src/cpu/o3/alpha_dyn_inst.hh
+++ b/src/cpu/o3/alpha_dyn_inst.hh
@@ -93,23 +93,31 @@ class AlphaDynInst : public BaseDynInst<Impl>
     void initVars();
 
   public:
+    /** Reads a miscellaneous register. */
     MiscReg readMiscReg(int misc_reg)
     {
         return this->cpu->readMiscReg(misc_reg, this->threadNumber);
     }
 
+    /** Reads a misc. register, including any side-effects the read
+     * might have as defined by the architecture.
+     */
     MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
     {
         return this->cpu->readMiscRegWithEffect(misc_reg, fault,
                                                 this->threadNumber);
     }
 
+    /** Sets a misc. register. */
     Fault setMiscReg(int misc_reg, const MiscReg &val)
     {
         this->instResult.integer = val;
         return this->cpu->setMiscReg(misc_reg, val, this->threadNumber);
     }
 
+    /** Sets a misc. register, including any side-effects the write
+     * might have as defined by the architecture.
+     */
     Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
     {
         return this->cpu->setMiscRegWithEffect(misc_reg, val,