Fixes to get MIPS_SE to compile.

[gem5.git] / src / cpu / o3 / bpred_unit_impl.hh

diff --git a/src/cpu/o3/bpred_unit_impl.hh b/src/cpu/o3/bpred_unit_impl.hh
index 0da02145bcb9f069aa6903e36393db67754ad0e7..dbc603082db32a16268b065e210e4d67919ed553 100644 (file)
--- a/src/cpu/o3/bpred_unit_impl.hh
+++ b/src/cpu/o3/bpred_unit_impl.hh
@@ -28,15 +28,12 @@
  * Authors: Kevin Lim
  */
 
-#include <list>
-#include <vector>
-
+#include "arch/types.hh"
+#include "arch/isa_traits.hh"
 #include "base/trace.hh"
 #include "base/traceflags.hh"
 #include "cpu/o3/bpred_unit.hh"
 
-using namespace std;
-
 template<class Impl>
 BPredUnit<Impl>::BPredUnit(Params *params)
   : BTB(params->BTBEntries,
@@ -159,7 +156,7 @@ BPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC, unsigned tid)
     void *bp_history = NULL;
 
     if (inst->isUncondCtrl()) {
-        DPRINTF(Fetch, "BranchPred: [tid:%i] Unconditional control.\n", tid);
+        DPRINTF(Fetch, "BranchPred: [tid:%i]: Unconditional control.\n", tid);
         pred_taken = true;
         // Tell the BP there was an unconditional branch.
         BPUncond(bp_history);
@@ -201,15 +198,20 @@ BPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC, unsigned tid)
             ++BTBLookups;
 
             if (inst->isCall()) {
-                RAS[tid].push(PC + sizeof(MachInst));
+#if ISA_HAS_DELAY_SLOT
+                Addr ras_pc = PC + (2 * sizeof(MachInst)); // Next Next PC
+#else
+                Addr ras_pc = PC + sizeof(MachInst); // Next PC
+#endif
+                RAS[tid].push(ras_pc);
 
                 // Record that it was a call so that the top RAS entry can
                 // be popped off if the speculation is incorrect.
                 predict_record.wasCall = true;
 
-                DPRINTF(Fetch, "BranchPred: [tid:%i] Instruction %#x was a call"
-                        ", adding %#x to the RAS.\n",
-                        tid, inst->readPC(), PC + sizeof(MachInst));
+                DPRINTF(Fetch, "BranchPred: [tid:%i]: Instruction %#x was a call"
+                        ", adding %#x to the RAS index: %i.\n",
+                        tid, inst->readPC(), ras_pc, RAS[tid].topIdx());
             }
 
             if (BTB.valid(PC, tid)) {
@@ -231,18 +233,9 @@ BPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC, unsigned tid)
         }
     }
 
-    if (pred_taken) {
-        // Set the PC and the instruction's predicted target.
-        PC = target;
-        inst->setPredTarg(target);
-    } else {
-        PC = PC + sizeof(MachInst);
-        inst->setPredTarg(PC);
-    }
-
     predHist[tid].push_front(predict_record);
 
-    DPRINTF(Fetch, "[tid:%i] predHist.size(): %i\n", tid, predHist[tid].size());
+    DPRINTF(Fetch, "[tid:%i]: predHist.size(): %i\n", tid, predHist[tid].size());
 
     return pred_taken;
 }
@@ -251,8 +244,8 @@ template <class Impl>
 void
 BPredUnit<Impl>::update(const InstSeqNum &done_sn, unsigned tid)
 {
-    DPRINTF(Fetch, "BranchPred: [tid:%i]: Commiting branches until sequence"
-            "number %lli.\n", tid, done_sn);
+    DPRINTF(Fetch, "BranchPred: [tid:%i]: Commiting branches until "
+            "[sn:%lli].\n", tid, done_sn);
 
     while (!predHist[tid].empty() &&
            predHist[tid].back().seqNum <= done_sn) {
@@ -282,7 +275,6 @@ BPredUnit<Impl>::squash(const InstSeqNum &squashed_sn, unsigned tid)
 
             RAS[tid].restore(pred_hist.front().RASIndex,
                              pred_hist.front().RASTarget);
-
         } else if (pred_hist.front().wasCall) {
             DPRINTF(Fetch, "BranchPred: [tid:%i]: Removing speculative entry "
                     "added to the RAS.\n",tid);