/*
- * Copyright (c) 2011 ARM Limited
+ * Copyright (c) 2011, 2016-2017 ARM Limited
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Kevin Lim
*/
#ifndef __CPU_O3_COMM_HH__
#include "cpu/inst_seq.hh"
#include "sim/faults.hh"
-// Typedef for physical register index type. Although the Impl would be the
-// most likely location for this, there are a few classes that need this
-// typedef yet are not templated on the Impl. For now it will be defined here.
-typedef short int PhysRegIndex;
-
/** Struct that defines the information passed from fetch to decode. */
template<class Impl>
struct DefaultFetchDefaultDecode {
int size;
DynInstPtr insts[Impl::MaxWidth];
-
- bool squash[Impl::MaxThreads];
- bool branchMispredict[Impl::MaxThreads];
DynInstPtr mispredictInst[Impl::MaxThreads];
- bool branchTaken[Impl::MaxThreads];
Addr mispredPC[Impl::MaxThreads];
- TheISA::PCState pc[Impl::MaxThreads];
InstSeqNum squashedSeqNum[Impl::MaxThreads];
+ TheISA::PCState pc[Impl::MaxThreads];
+ bool squash[Impl::MaxThreads];
+ bool branchMispredict[Impl::MaxThreads];
+ bool branchTaken[Impl::MaxThreads];
bool includeSquashInst[Impl::MaxThreads];
};
struct TimeBufStruct {
typedef typename Impl::DynInstPtr DynInstPtr;
struct decodeComm {
+ TheISA::PCState nextPC;
+ DynInstPtr mispredictInst;
+ DynInstPtr squashInst;
+ InstSeqNum doneSeqNum;
+ Addr mispredPC;
+ uint64_t branchAddr;
+ unsigned branchCount;
bool squash;
bool predIncorrect;
- uint64_t branchAddr;
-
- InstSeqNum doneSeqNum;
-
- // @todo: Might want to package this kind of branch stuff into a single
- // struct as it is used pretty frequently.
bool branchMispredict;
- DynInstPtr mispredictInst;
bool branchTaken;
- Addr mispredPC;
- TheISA::PCState nextPC;
- DynInstPtr squashInst;
- unsigned branchCount;
};
decodeComm decodeInfo[Impl::MaxThreads];
struct iewComm {
// Also eventually include skid buffer space.
- bool usedIQ;
unsigned freeIQEntries;
- bool usedLSQ;
- unsigned freeLSQEntries;
+ unsigned freeLQEntries;
+ unsigned freeSQEntries;
+ unsigned dispatchedToLQ;
+ unsigned dispatchedToSQ;
unsigned iqCount;
unsigned ldstqCount;
unsigned dispatched;
- unsigned dispatchedToLSQ;
+ bool usedIQ;
+ bool usedLSQ;
};
iewComm iewInfo[Impl::MaxThreads];
struct commitComm {
-
- /////////////// For Decode, IEW, Rename, Fetch ///////////
- bool squash;
- bool robSquashing;
-
- ////////// For Fetch & IEW /////////////
- // Represents the instruction that has either been retired or
- // squashed. Similar to having a single bus that broadcasts the
- // retired or squashed sequence number.
- InstSeqNum doneSeqNum;
-
- ////////////// For Rename /////////////////
- // Rename should re-read number of free rob entries
- bool usedROB;
- // Notify Rename that the ROB is empty
- bool emptyROB;
- // Tell Rename how many free entries it has in the ROB
- unsigned freeROBEntries;
-
-
- ///////////// For Fetch //////////////////
- // Provide fetch the instruction that mispredicted, if this
- // pointer is not-null a misprediction occured
- DynInstPtr mispredictInst;
- // Was the branch taken or not
- bool branchTaken;
- // The pc of the next instruction to execute. This is the next
- // instruction for a branch mispredict, but the same instruction for
- // order violation and the like
- TheISA::PCState pc;
-
- // Instruction that caused the a non-mispredict squash
- DynInstPtr squashInst;
- // If an interrupt is pending and fetch should stall
- bool interruptPending;
- // If the interrupt ended up being cleared before being handled
- bool clearInterrupt;
-
- //////////// For IEW //////////////////
- // Communication specifically to the IQ to tell the IQ that it can
- // schedule a non-speculative instruction.
- InstSeqNum nonSpecSeqNum;
-
- // Hack for now to send back an uncached access to the IEW stage.
- bool uncached;
- DynInstPtr uncachedLoad;
+ /////////////////////////////////////////////////////////////////////
+ // This code has been re-structured for better packing of variables
+ // instead of by stage which is the more logical way to arrange the
+ // data.
+ // F = Fetch
+ // D = Decode
+ // I = IEW
+ // R = Rename
+ // As such each member is annotated with who consumes it
+ // e.g. bool variable name // *F,R for Fetch and Rename
+ /////////////////////////////////////////////////////////////////////
+
+ /// The pc of the next instruction to execute. This is the next
+ /// instruction for a branch mispredict, but the same instruction for
+ /// order violation and the like
+ TheISA::PCState pc; // *F
+
+ /// Provide fetch the instruction that mispredicted, if this
+ /// pointer is not-null a misprediction occured
+ DynInstPtr mispredictInst; // *F
+
+ /// Instruction that caused the a non-mispredict squash
+ DynInstPtr squashInst; // *F
+
+ /// Hack for now to send back a strictly ordered access to the
+ /// IEW stage.
+ DynInstPtr strictlyOrderedLoad; // *I
+
+ /// Communication specifically to the IQ to tell the IQ that it can
+ /// schedule a non-speculative instruction.
+ InstSeqNum nonSpecSeqNum; // *I
+
+ /// Represents the instruction that has either been retired or
+ /// squashed. Similar to having a single bus that broadcasts the
+ /// retired or squashed sequence number.
+ InstSeqNum doneSeqNum; // *F, I
+
+ /// Tell Rename how many free entries it has in the ROB
+ unsigned freeROBEntries; // *R
+
+ bool squash; // *F, D, R, I
+ bool robSquashing; // *F, D, R, I
+
+ /// Rename should re-read number of free rob entries
+ bool usedROB; // *R
+
+ /// Notify Rename that the ROB is empty
+ bool emptyROB; // *R
+
+ /// Was the branch taken or not
+ bool branchTaken; // *F
+ /// If an interrupt is pending and fetch should stall
+ bool interruptPending; // *F
+ /// If the interrupt ended up being cleared before being handled
+ bool clearInterrupt; // *F
+
+ /// Hack for now to send back an strictly ordered access to
+ /// the IEW stage.
+ bool strictlyOrdered; // *I
};
bool renameUnblock[Impl::MaxThreads];
bool iewBlock[Impl::MaxThreads];
bool iewUnblock[Impl::MaxThreads];
- bool commitBlock[Impl::MaxThreads];
- bool commitUnblock[Impl::MaxThreads];
};
#endif //__CPU_O3_COMM_HH__
projects / gem5.git / blobdiff