/*
- * Copyright (c) 2011 ARM Limited
+ * Copyright (c) 2011-2013 ARM Limited
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
* The license below extends only to copyright in the software and shall
/**
* IcachePort class for instruction fetch.
*/
- class IcachePort : public CpuPort
+ class IcachePort : public MasterPort
{
protected:
/** Pointer to fetch. */
public:
/** Default constructor. */
IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
- : CpuPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
+ : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
{ }
protected:
/** Timing version of receive. Handles setting fetch to the
* proper status to start fetching. */
virtual bool recvTimingResp(PacketPtr pkt);
- virtual void recvTimingSnoopReq(PacketPtr pkt) { }
/** Handles doing a retry of a failed fetch. */
- virtual void recvRetry();
+ virtual void recvReqRetry();
};
/**
* DcachePort class for the load/store queue.
*/
- class DcachePort : public CpuPort
+ class DcachePort : public MasterPort
{
protected:
/** Pointer to LSQ. */
LSQ<Impl> *lsq;
+ FullO3CPU<Impl> *cpu;
public:
/** Default constructor. */
DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
- : CpuPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq)
+ : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq),
+ cpu(_cpu)
{ }
protected:
virtual bool recvTimingResp(PacketPtr pkt);
virtual void recvTimingSnoopReq(PacketPtr pkt);
+ virtual void recvFunctionalSnoop(PacketPtr pkt)
+ {
+ // @todo: Is there a need for potential invalidation here?
+ }
+
/** Handles doing a retry of the previous send. */
- virtual void recvRetry();
+ virtual void recvReqRetry();
/**
* As this CPU requires snooping to maintain the load store queue
tickEvent.squash();
}
- class ActivateThreadEvent : public Event
- {
- private:
- /** Number of Thread to Activate */
- ThreadID tid;
-
- /** Pointer to the CPU. */
- FullO3CPU<Impl> *cpu;
-
- public:
- /** Constructs the event. */
- ActivateThreadEvent();
-
- /** Initialize Event */
- void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
-
- /** Processes the event, calling activateThread() on the CPU. */
- void process();
-
- /** Returns the description of the event. */
- const char *description() const;
- };
-
- /** Schedule thread to activate , regardless of its current state. */
- void
- scheduleActivateThreadEvent(ThreadID tid, Cycles delay)
- {
- // Schedule thread to activate, regardless of its current state.
- if (activateThreadEvent[tid].squashed())
- reschedule(activateThreadEvent[tid],
- clockEdge(delay));
- else if (!activateThreadEvent[tid].scheduled()) {
- Tick when = clockEdge(delay);
-
- // Check if the deallocateEvent is also scheduled, and make
- // sure they do not happen at same time causing a sleep that
- // is never woken from.
- if (deallocateContextEvent[tid].scheduled() &&
- deallocateContextEvent[tid].when() == when) {
- when++;
- }
-
- schedule(activateThreadEvent[tid], when);
- }
- }
-
- /** Unschedule actiavte thread event, regardless of its current state. */
- void
- unscheduleActivateThreadEvent(ThreadID tid)
- {
- if (activateThreadEvent[tid].scheduled())
- activateThreadEvent[tid].squash();
- }
-
- /** The tick event used for scheduling CPU ticks. */
- ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
-
- class DeallocateContextEvent : public Event
- {
- private:
- /** Number of Thread to deactivate */
- ThreadID tid;
-
- /** Should the thread be removed from the CPU? */
- bool remove;
-
- /** Pointer to the CPU. */
- FullO3CPU<Impl> *cpu;
-
- public:
- /** Constructs the event. */
- DeallocateContextEvent();
-
- /** Initialize Event */
- void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
-
- /** Processes the event, calling activateThread() on the CPU. */
- void process();
-
- /** Sets whether the thread should also be removed from the CPU. */
- void setRemove(bool _remove) { remove = _remove; }
-
- /** Returns the description of the event. */
- const char *description() const;
- };
-
- /** Schedule cpu to deallocate thread context.*/
- void
- scheduleDeallocateContextEvent(ThreadID tid, bool remove, Cycles delay)
- {
- // Schedule thread to activate, regardless of its current state.
- if (deallocateContextEvent[tid].squashed())
- reschedule(deallocateContextEvent[tid],
- clockEdge(delay));
- else if (!deallocateContextEvent[tid].scheduled())
- schedule(deallocateContextEvent[tid],
- clockEdge(delay));
- }
+ /**
+ * Check if the pipeline has drained and signal drain done.
+ *
+ * This method checks if a drain has been requested and if the CPU
+ * has drained successfully (i.e., there are no instructions in
+ * the pipeline). If the CPU has drained, it deschedules the tick
+ * event and signals the drain manager.
+ *
+ * @return False if a drain hasn't been requested or the CPU
+ * hasn't drained, true otherwise.
+ */
+ bool tryDrain();
- /** Unschedule thread deallocation in CPU */
- void
- unscheduleDeallocateContextEvent(ThreadID tid)
- {
- if (deallocateContextEvent[tid].scheduled())
- deallocateContextEvent[tid].squash();
- }
+ /**
+ * Perform sanity checks after a drain.
+ *
+ * This method is called from drain() when it has determined that
+ * the CPU is fully drained when gem5 is compiled with the NDEBUG
+ * macro undefined. The intention of this method is to do more
+ * extensive tests than the isDrained() method to weed out any
+ * draining bugs.
+ */
+ void drainSanityCheck() const;
- /** The tick event used for scheduling CPU ticks. */
- DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
+ /** Check if a system is in a drained state. */
+ bool isDrained() const;
public:
/** Constructs a CPU with the given parameters. */
~FullO3CPU();
/** Registers statistics. */
- void regStats();
+ void regStats() override;
+
+ ProbePointArg<PacketPtr> *ppInstAccessComplete;
+ ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete;
+
+ /** Register probe points. */
+ void regProbePoints() override;
void demapPage(Addr vaddr, uint64_t asn)
{
void tick();
/** Initialize the CPU */
- void init();
+ void init() override;
- void startup();
+ void startup() override;
/** Returns the Number of Active Threads in the CPU */
int numActiveThreads()
void removeThread(ThreadID tid);
/** Count the Total Instructions Committed in the CPU. */
- virtual Counter totalInsts() const;
+ Counter totalInsts() const override;
/** Count the Total Ops (including micro ops) committed in the CPU. */
- virtual Counter totalOps() const;
+ Counter totalOps() const override;
/** Add Thread to Active Threads List. */
- void activateContext(ThreadID tid, Cycles delay);
+ void activateContext(ThreadID tid) override;
/** Remove Thread from Active Threads List */
- void suspendContext(ThreadID tid);
-
- /** Remove Thread from Active Threads List &&
- * Possibly Remove Thread Context from CPU.
- */
- bool scheduleDeallocateContext(ThreadID tid, bool remove,
- Cycles delay = Cycles(1));
+ void suspendContext(ThreadID tid) override;
/** Remove Thread from Active Threads List &&
* Remove Thread Context from CPU.
*/
- void haltContext(ThreadID tid);
-
- /** Activate a Thread When CPU Resources are Available. */
- void activateWhenReady(ThreadID tid);
-
- /** Add or Remove a Thread Context in the CPU. */
- void doContextSwitch();
+ void haltContext(ThreadID tid) override;
/** Update The Order In Which We Process Threads. */
void updateThreadPriority();
- /** Serialize state. */
- virtual void serialize(std::ostream &os);
+ /** Is the CPU draining? */
+ bool isDraining() const { return drainState() == DrainState::Draining; }
- /** Unserialize from a checkpoint. */
- virtual void unserialize(Checkpoint *cp, const std::string §ion);
+ void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
+ void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
public:
/** Executes a syscall.
* @todo: Determine if this needs to be virtual.
*/
- void syscall(int64_t callnum, ThreadID tid);
+ void syscall(int64_t callnum, ThreadID tid, Fault *fault);
/** Starts draining the CPU's pipeline of all instructions in
* order to stop all memory accesses. */
- unsigned int drain(DrainManager *drain_manager);
+ DrainState drain() override;
/** Resumes execution after a drain. */
- void drainResume();
+ void drainResume() override;
- /** Signals to this CPU that a stage has completed switching out. */
- void signalDrained();
+ /**
+ * Commit has reached a safe point to drain a thread.
+ *
+ * Commit calls this method to inform the pipeline that it has
+ * reached a point where it is not executed microcode and is about
+ * to squash uncommitted instructions to fully drain the pipeline.
+ */
+ void commitDrained(ThreadID tid);
/** Switches out this CPU. */
- virtual void switchOut();
+ void switchOut() override;
/** Takes over from another CPU. */
- virtual void takeOverFrom(BaseCPU *oldCPU);
+ void takeOverFrom(BaseCPU *oldCPU) override;
+
+ void verifyMemoryMode() const override;
/** Get the current instruction sequence number, and increment it. */
InstSeqNum getAndIncrementInstSeq()
{ return globalSeqNum++; }
/** Traps to handle given fault. */
- void trap(Fault fault, ThreadID tid, StaticInstPtr inst);
+ void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst);
/** HW return from error interrupt. */
Fault hwrei(ThreadID tid);
Fault getInterrupts();
/** Processes any an interrupt fault. */
- void processInterrupts(Fault interrupt);
+ void processInterrupts(const Fault &interrupt);
/** Halts the CPU. */
void halt() { panic("Halt not implemented!\n"); }
- /** Check if this address is a valid instruction address. */
- bool validInstAddr(Addr addr) { return true; }
-
- /** Check if this address is a valid data address. */
- bool validDataAddr(Addr addr) { return true; }
-
/** Register accessors. Index refers to the physical register index. */
/** Reads a miscellaneous register. */
- TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid);
+ TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid) const;
/** Reads a misc. register, including any side effects the read
* might have as defined by the architecture.
TheISA::FloatRegBits readFloatRegBits(int reg_idx);
+ TheISA::CCReg readCCReg(int reg_idx);
+
void setIntReg(int reg_idx, uint64_t val);
void setFloatReg(int reg_idx, TheISA::FloatReg val);
void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
+ void setCCReg(int reg_idx, TheISA::CCReg val);
+
uint64_t readArchIntReg(int reg_idx, ThreadID tid);
float readArchFloatReg(int reg_idx, ThreadID tid);
uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
+ TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid);
+
/** Architectural register accessors. Looks up in the commit
* rename table to obtain the true physical index of the
* architected register first, then accesses that physical
void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
+ void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid);
+
/** Sets the commit PC state of a specific thread. */
void pcState(const TheISA::PCState &newPCState, ThreadID tid);
typename CPUPolicy::Commit commit;
/** The register file. */
- typename CPUPolicy::RegFile regFile;
+ PhysRegFile regFile;
/** The free list. */
typename CPUPolicy::FreeList freeList;
/** Wakes the CPU, rescheduling the CPU if it's not already active. */
void wakeCPU();
- virtual void wakeup();
+ virtual void wakeup(ThreadID tid) override;
/** Gets a free thread id. Use if thread ids change across system. */
ThreadID getFreeTid();
/** Pointer to the system. */
System *system;
- /** DrainManager to notify when draining has completed. */
- DrainManager *drainManager;
-
- /** Counter of how many stages have completed draining. */
- int drainCount;
-
/** Pointers to all of the threads in the CPU. */
std::vector<Thread *> thread;
- /** Is there a context switch pending? */
- bool contextSwitch;
-
/** Threads Scheduled to Enter CPU */
std::list<int> cpuWaitList;
/** CPU read function, forwards read to LSQ. */
Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
- uint8_t *data, int load_idx)
+ int load_idx)
{
- return this->iew.ldstQueue.read(req, sreqLow, sreqHigh,
- data, load_idx);
+ return this->iew.ldstQueue.read(req, sreqLow, sreqHigh, load_idx);
}
/** CPU write function, forwards write to LSQ. */
}
/** Used by the fetch unit to get a hold of the instruction port. */
- virtual CpuPort &getInstPort() { return icachePort; }
+ MasterPort &getInstPort() override { return icachePort; }
/** Get the dcache port (used to find block size for translations). */
- virtual CpuPort &getDataPort() { return dcachePort; }
+ MasterPort &getDataPort() override { return dcachePort; }
/** Stat for total number of times the CPU is descheduled. */
Stats::Scalar timesIdled;
Stats::Vector committedInsts;
/** Stat for the number of committed ops (including micro ops) per thread. */
Stats::Vector committedOps;
- /** Stat for the total number of committed instructions. */
- Stats::Scalar totalCommittedInsts;
/** Stat for the CPI per thread. */
Stats::Formula cpi;
/** Stat for the total CPI. */
//number of float register file accesses
Stats::Scalar fpRegfileReads;
Stats::Scalar fpRegfileWrites;
+ //number of CC register file accesses
+ Stats::Scalar ccRegfileReads;
+ Stats::Scalar ccRegfileWrites;
//number of misc
Stats::Scalar miscRegfileReads;
Stats::Scalar miscRegfileWrites;
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