/*
+ * Copyright (c) 2011-2013 ARM Limited
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2011 Regents of the University of California
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Authors: Kevin Lim
* Korey Sewell
+ * Rick Strong
*/
#ifndef __CPU_O3_CPU_HH__
#include "arch/types.hh"
#include "base/statistics.hh"
-#include "base/timebuf.hh"
-#include "config/full_system.hh"
-#include "config/use_checker.hh"
-#include "cpu/activity.hh"
-#include "cpu/base.hh"
-#include "cpu/simple_thread.hh"
+#include "config/the_isa.hh"
#include "cpu/o3/comm.hh"
#include "cpu/o3/cpu_policy.hh"
#include "cpu/o3/scoreboard.hh"
#include "cpu/o3/thread_state.hh"
+#include "cpu/activity.hh"
+#include "cpu/base.hh"
+#include "cpu/simple_thread.hh"
+#include "cpu/timebuf.hh"
//#include "cpu/o3/thread_context.hh"
-#include "sim/process.hh"
-
#include "params/DerivO3CPU.hh"
+#include "sim/process.hh"
template <class>
class Checker;
class MemObject;
class Process;
-class BaseCPUParams;
+struct BaseCPUParams;
class BaseO3CPU : public BaseCPU
{
SwitchedOut
};
- TheISA::ITB * itb;
- TheISA::DTB * dtb;
+ TheISA::TLB * itb;
+ TheISA::TLB * dtb;
/** Overall CPU status. */
Status _status;
- /** Per-thread status in CPU, used for SMT. */
- Status _threadStatus[Impl::MaxThreads];
-
private:
+
+ /**
+ * IcachePort class for instruction fetch.
+ */
+ class IcachePort : public MasterPort
+ {
+ protected:
+ /** Pointer to fetch. */
+ DefaultFetch<Impl> *fetch;
+
+ public:
+ /** Default constructor. */
+ IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
+ : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
+ { }
+
+ protected:
+
+ /** Timing version of receive. Handles setting fetch to the
+ * proper status to start fetching. */
+ virtual bool recvTimingResp(PacketPtr pkt);
+
+ /** Handles doing a retry of a failed fetch. */
+ virtual void recvReqRetry();
+ };
+
+ /**
+ * DcachePort class for the load/store queue.
+ */
+ class DcachePort : public MasterPort
+ {
+ protected:
+
+ /** Pointer to LSQ. */
+ LSQ<Impl> *lsq;
+ FullO3CPU<Impl> *cpu;
+
+ public:
+ /** Default constructor. */
+ DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
+ : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq),
+ cpu(_cpu)
+ { }
+
+ protected:
+
+ /** Timing version of receive. Handles writing back and
+ * completing the load or store that has returned from
+ * memory. */
+ virtual bool recvTimingResp(PacketPtr pkt);
+ virtual void recvTimingSnoopReq(PacketPtr pkt);
+
+ virtual void recvFunctionalSnoop(PacketPtr pkt)
+ {
+ // @todo: Is there a need for potential invalidation here?
+ }
+
+ /** Handles doing a retry of the previous send. */
+ virtual void recvReqRetry();
+
+ /**
+ * As this CPU requires snooping to maintain the load store queue
+ * change the behaviour from the base CPU port.
+ *
+ * @return true since we have to snoop
+ */
+ virtual bool isSnooping() const { return true; }
+ };
+
class TickEvent : public Event
{
private:
TickEvent tickEvent;
/** Schedule tick event, regardless of its current state. */
- void scheduleTickEvent(int delay)
+ void scheduleTickEvent(Cycles delay)
{
if (tickEvent.squashed())
- reschedule(tickEvent, nextCycle(curTick + ticks(delay)));
+ reschedule(tickEvent, clockEdge(delay));
else if (!tickEvent.scheduled())
- schedule(tickEvent, nextCycle(curTick + ticks(delay)));
+ schedule(tickEvent, clockEdge(delay));
}
/** Unschedule tick event, regardless of its current state. */
tickEvent.squash();
}
- class ActivateThreadEvent : public Event
- {
- private:
- /** Number of Thread to Activate */
- int tid;
-
- /** Pointer to the CPU. */
- FullO3CPU<Impl> *cpu;
-
- public:
- /** Constructs the event. */
- ActivateThreadEvent();
-
- /** Initialize Event */
- void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
-
- /** Processes the event, calling activateThread() on the CPU. */
- void process();
-
- /** Returns the description of the event. */
- const char *description() const;
- };
-
- /** Schedule thread to activate , regardless of its current state. */
- void scheduleActivateThreadEvent(int tid, int delay)
- {
- // Schedule thread to activate, regardless of its current state.
- if (activateThreadEvent[tid].squashed())
- reschedule(activateThreadEvent[tid],
- nextCycle(curTick + ticks(delay)));
- else if (!activateThreadEvent[tid].scheduled())
- schedule(activateThreadEvent[tid],
- nextCycle(curTick + ticks(delay)));
- }
-
- /** Unschedule actiavte thread event, regardless of its current state. */
- void unscheduleActivateThreadEvent(int tid)
- {
- if (activateThreadEvent[tid].scheduled())
- activateThreadEvent[tid].squash();
- }
-
- /** The tick event used for scheduling CPU ticks. */
- ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
-
- class DeallocateContextEvent : public Event
- {
- private:
- /** Number of Thread to deactivate */
- int tid;
-
- /** Should the thread be removed from the CPU? */
- bool remove;
-
- /** Pointer to the CPU. */
- FullO3CPU<Impl> *cpu;
-
- public:
- /** Constructs the event. */
- DeallocateContextEvent();
-
- /** Initialize Event */
- void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
-
- /** Processes the event, calling activateThread() on the CPU. */
- void process();
-
- /** Sets whether the thread should also be removed from the CPU. */
- void setRemove(bool _remove) { remove = _remove; }
-
- /** Returns the description of the event. */
- const char *description() const;
- };
-
- /** Schedule cpu to deallocate thread context.*/
- void scheduleDeallocateContextEvent(int tid, bool remove, int delay)
- {
- // Schedule thread to activate, regardless of its current state.
- if (deallocateContextEvent[tid].squashed())
- reschedule(deallocateContextEvent[tid],
- nextCycle(curTick + ticks(delay)));
- else if (!deallocateContextEvent[tid].scheduled())
- schedule(deallocateContextEvent[tid],
- nextCycle(curTick + ticks(delay)));
- }
-
- /** Unschedule thread deallocation in CPU */
- void unscheduleDeallocateContextEvent(int tid)
- {
- if (deallocateContextEvent[tid].scheduled())
- deallocateContextEvent[tid].squash();
- }
+ /**
+ * Check if the pipeline has drained and signal drain done.
+ *
+ * This method checks if a drain has been requested and if the CPU
+ * has drained successfully (i.e., there are no instructions in
+ * the pipeline). If the CPU has drained, it deschedules the tick
+ * event and signals the drain manager.
+ *
+ * @return False if a drain hasn't been requested or the CPU
+ * hasn't drained, true otherwise.
+ */
+ bool tryDrain();
+
+ /**
+ * Perform sanity checks after a drain.
+ *
+ * This method is called from drain() when it has determined that
+ * the CPU is fully drained when gem5 is compiled with the NDEBUG
+ * macro undefined. The intention of this method is to do more
+ * extensive tests than the isDrained() method to weed out any
+ * draining bugs.
+ */
+ void drainSanityCheck() const;
- /** The tick event used for scheduling CPU ticks. */
- DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
+ /** Check if a system is in a drained state. */
+ bool isDrained() const;
public:
/** Constructs a CPU with the given parameters. */
~FullO3CPU();
/** Registers statistics. */
- void regStats();
+ void regStats() override;
+
+ ProbePointArg<PacketPtr> *ppInstAccessComplete;
+ ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete;
+
+ /** Register probe points. */
+ void regProbePoints() override;
void demapPage(Addr vaddr, uint64_t asn)
{
this->dtb->demapPage(vaddr, asn);
}
- /** Returns a specific port. */
- Port *getPort(const std::string &if_name, int idx);
-
/** Ticks CPU, calling tick() on each stage, and checking the overall
* activity to see if the CPU should deschedule itself.
*/
void tick();
/** Initialize the CPU */
- void init();
+ void init() override;
+
+ void startup() override;
/** Returns the Number of Active Threads in the CPU */
int numActiveThreads()
{ return activeThreads.size(); }
/** Add Thread to Active Threads List */
- void activateThread(unsigned tid);
+ void activateThread(ThreadID tid);
/** Remove Thread from Active Threads List */
- void deactivateThread(unsigned tid);
+ void deactivateThread(ThreadID tid);
/** Setup CPU to insert a thread's context */
- void insertThread(unsigned tid);
+ void insertThread(ThreadID tid);
/** Remove all of a thread's context from CPU */
- void removeThread(unsigned tid);
+ void removeThread(ThreadID tid);
/** Count the Total Instructions Committed in the CPU. */
- virtual Counter totalInstructions() const
- {
- Counter total(0);
-
- for (int i=0; i < thread.size(); i++)
- total += thread[i]->numInst;
+ Counter totalInsts() const override;
- return total;
- }
+ /** Count the Total Ops (including micro ops) committed in the CPU. */
+ Counter totalOps() const override;
/** Add Thread to Active Threads List. */
- void activateContext(int tid, int delay);
+ void activateContext(ThreadID tid) override;
/** Remove Thread from Active Threads List */
- void suspendContext(int tid);
-
- /** Remove Thread from Active Threads List &&
- * Possibly Remove Thread Context from CPU.
- */
- bool deallocateContext(int tid, bool remove, int delay = 1);
+ void suspendContext(ThreadID tid) override;
/** Remove Thread from Active Threads List &&
* Remove Thread Context from CPU.
*/
- void haltContext(int tid);
-
- /** Activate a Thread When CPU Resources are Available. */
- void activateWhenReady(int tid);
-
- /** Add or Remove a Thread Context in the CPU. */
- void doContextSwitch();
+ void haltContext(ThreadID tid) override;
/** Update The Order In Which We Process Threads. */
void updateThreadPriority();
- /** Serialize state. */
- virtual void serialize(std::ostream &os);
+ /** Is the CPU draining? */
+ bool isDraining() const { return drainState() == DrainState::Draining; }
- /** Unserialize from a checkpoint. */
- virtual void unserialize(Checkpoint *cp, const std::string §ion);
+ void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
+ void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
public:
-#if !FULL_SYSTEM
/** Executes a syscall.
* @todo: Determine if this needs to be virtual.
*/
- void syscall(int64_t callnum, int tid);
-#endif
+ void syscall(int64_t callnum, ThreadID tid, Fault *fault);
/** Starts draining the CPU's pipeline of all instructions in
* order to stop all memory accesses. */
- virtual unsigned int drain(Event *drain_event);
+ DrainState drain() override;
/** Resumes execution after a drain. */
- virtual void resume();
-
- /** Signals to this CPU that a stage has completed switching out. */
- void signalDrained();
+ void drainResume() override;
+
+ /**
+ * Commit has reached a safe point to drain a thread.
+ *
+ * Commit calls this method to inform the pipeline that it has
+ * reached a point where it is not executed microcode and is about
+ * to squash uncommitted instructions to fully drain the pipeline.
+ */
+ void commitDrained(ThreadID tid);
/** Switches out this CPU. */
- virtual void switchOut();
+ void switchOut() override;
/** Takes over from another CPU. */
- virtual void takeOverFrom(BaseCPU *oldCPU);
+ void takeOverFrom(BaseCPU *oldCPU) override;
+
+ void verifyMemoryMode() const override;
/** Get the current instruction sequence number, and increment it. */
InstSeqNum getAndIncrementInstSeq()
{ return globalSeqNum++; }
/** Traps to handle given fault. */
- void trap(Fault fault, unsigned tid);
+ void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst);
-#if FULL_SYSTEM
/** HW return from error interrupt. */
- Fault hwrei(unsigned tid);
+ Fault hwrei(ThreadID tid);
- bool simPalCheck(int palFunc, unsigned tid);
+ bool simPalCheck(int palFunc, ThreadID tid);
/** Returns the Fault for any valid interrupt. */
Fault getInterrupts();
/** Processes any an interrupt fault. */
- void processInterrupts(Fault interrupt);
+ void processInterrupts(const Fault &interrupt);
/** Halts the CPU. */
void halt() { panic("Halt not implemented!\n"); }
- /** Update the Virt and Phys ports of all ThreadContexts to
- * reflect change in memory connections. */
- void updateMemPorts();
-
- /** Check if this address is a valid instruction address. */
- bool validInstAddr(Addr addr) { return true; }
-
- /** Check if this address is a valid data address. */
- bool validDataAddr(Addr addr) { return true; }
-
- /** Get instruction asid. */
- int getInstAsid(unsigned tid)
- { return regFile.miscRegs[tid].getInstAsid(); }
-
- /** Get data asid. */
- int getDataAsid(unsigned tid)
- { return regFile.miscRegs[tid].getDataAsid(); }
-#else
- /** Get instruction asid. */
- int getInstAsid(unsigned tid)
- { return thread[tid]->getInstAsid(); }
-
- /** Get data asid. */
- int getDataAsid(unsigned tid)
- { return thread[tid]->getDataAsid(); }
-
-#endif
-
/** Register accessors. Index refers to the physical register index. */
/** Reads a miscellaneous register. */
- TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid);
+ TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid) const;
/** Reads a misc. register, including any side effects the read
* might have as defined by the architecture.
*/
- TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
+ TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
/** Sets a miscellaneous register. */
- void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, unsigned tid);
+ void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
+ ThreadID tid);
/** Sets a misc. register, including any side effects the write
* might have as defined by the architecture.
*/
void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
- unsigned tid);
+ ThreadID tid);
uint64_t readIntReg(int reg_idx);
TheISA::FloatReg readFloatReg(int reg_idx);
- TheISA::FloatReg readFloatReg(int reg_idx, int width);
-
TheISA::FloatRegBits readFloatRegBits(int reg_idx);
- TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width);
+ TheISA::CCReg readCCReg(int reg_idx);
void setIntReg(int reg_idx, uint64_t val);
void setFloatReg(int reg_idx, TheISA::FloatReg val);
- void setFloatReg(int reg_idx, TheISA::FloatReg val, int width);
-
void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
- void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width);
+ void setCCReg(int reg_idx, TheISA::CCReg val);
- uint64_t readArchIntReg(int reg_idx, unsigned tid);
+ uint64_t readArchIntReg(int reg_idx, ThreadID tid);
- float readArchFloatRegSingle(int reg_idx, unsigned tid);
+ float readArchFloatReg(int reg_idx, ThreadID tid);
- double readArchFloatRegDouble(int reg_idx, unsigned tid);
+ uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
- uint64_t readArchFloatRegInt(int reg_idx, unsigned tid);
+ TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid);
/** Architectural register accessors. Looks up in the commit
* rename table to obtain the true physical index of the
* architected register first, then accesses that physical
* register.
*/
- void setArchIntReg(int reg_idx, uint64_t val, unsigned tid);
+ void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
- void setArchFloatRegSingle(int reg_idx, float val, unsigned tid);
+ void setArchFloatReg(int reg_idx, float val, ThreadID tid);
- void setArchFloatRegDouble(int reg_idx, double val, unsigned tid);
+ void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
- void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid);
+ void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid);
- /** Reads the commit PC of a specific thread. */
- Addr readPC(unsigned tid);
+ /** Sets the commit PC state of a specific thread. */
+ void pcState(const TheISA::PCState &newPCState, ThreadID tid);
- /** Sets the commit PC of a specific thread. */
- void setPC(Addr new_PC, unsigned tid);
+ /** Reads the commit PC state of a specific thread. */
+ TheISA::PCState pcState(ThreadID tid);
- /** Reads the commit micro PC of a specific thread. */
- Addr readMicroPC(unsigned tid);
+ /** Reads the commit PC of a specific thread. */
+ Addr instAddr(ThreadID tid);
- /** Sets the commmit micro PC of a specific thread. */
- void setMicroPC(Addr new_microPC, unsigned tid);
+ /** Reads the commit micro PC of a specific thread. */
+ MicroPC microPC(ThreadID tid);
/** Reads the next PC of a specific thread. */
- Addr readNextPC(unsigned tid);
-
- /** Sets the next PC of a specific thread. */
- void setNextPC(Addr val, unsigned tid);
-
- /** Reads the next NPC of a specific thread. */
- Addr readNextNPC(unsigned tid);
-
- /** Sets the next NPC of a specific thread. */
- void setNextNPC(Addr val, unsigned tid);
-
- /** Reads the commit next micro PC of a specific thread. */
- Addr readNextMicroPC(unsigned tid);
-
- /** Sets the commit next micro PC of a specific thread. */
- void setNextMicroPC(Addr val, unsigned tid);
+ Addr nextInstAddr(ThreadID tid);
/** Initiates a squash of all in-flight instructions for a given
* thread. The source of the squash is an external update of
* state through the TC.
*/
- void squashFromTC(unsigned tid);
+ void squashFromTC(ThreadID tid);
/** Function to add instruction onto the head of the list of the
* instructions. Used when new instructions are fetched.
ListIt addInst(DynInstPtr &inst);
/** Function to tell the CPU that an instruction has completed. */
- void instDone(unsigned tid);
-
- /** Add Instructions to the CPU Remove List*/
- void addToRemoveList(DynInstPtr &inst);
+ void instDone(ThreadID tid, DynInstPtr &inst);
/** Remove an instruction from the front end of the list. There's
* no restriction on location of the instruction.
/** Remove all instructions that are not currently in the ROB.
* There's also an option to not squash delay slot instructions.*/
- void removeInstsNotInROB(unsigned tid);
+ void removeInstsNotInROB(ThreadID tid);
/** Remove all instructions younger than the given sequence number. */
- void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);
+ void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
/** Removes the instruction pointed to by the iterator. */
- inline void squashInstIt(const ListIt &instIt, const unsigned &tid);
+ inline void squashInstIt(const ListIt &instIt, ThreadID tid);
/** Cleans up all instructions on the remove list. */
void cleanUpRemovedInsts();
typename CPUPolicy::Commit commit;
/** The register file. */
- typename CPUPolicy::RegFile regFile;
+ PhysRegFile regFile;
/** The free list. */
typename CPUPolicy::FreeList freeList;
typename CPUPolicy::ROB rob;
/** Active Threads List */
- std::list<unsigned> activeThreads;
+ std::list<ThreadID> activeThreads;
/** Integer Register Scoreboard */
Scoreboard scoreboard;
+ std::vector<TheISA::ISA *> isa;
+
+ /** Instruction port. Note that it has to appear after the fetch stage. */
+ IcachePort icachePort;
+
+ /** Data port. Note that it has to appear after the iew stages */
+ DcachePort dcachePort;
+
public:
/** Enum to give each stage a specific index, so when calling
* activateStage() or deactivateStage(), they can specify which stage
/** Wakes the CPU, rescheduling the CPU if it's not already active. */
void wakeCPU();
-#if FULL_SYSTEM
- virtual void wakeup();
-#endif
+ virtual void wakeup(ThreadID tid) override;
/** Gets a free thread id. Use if thread ids change across system. */
- int getFreeTid();
+ ThreadID getFreeTid();
public:
/** Returns a pointer to a thread context. */
- ThreadContext *tcBase(unsigned tid)
+ ThreadContext *
+ tcBase(ThreadID tid)
{
return thread[tid]->getTC();
}
/** The global sequence number counter. */
InstSeqNum globalSeqNum;//[Impl::MaxThreads];
-#if USE_CHECKER
/** Pointer to the checker, which can dynamically verify
* instruction results at run time. This can be set to NULL if it
* is not being used.
*/
- Checker<DynInstPtr> *checker;
-#endif
+ Checker<Impl> *checker;
-#if FULL_SYSTEM
/** Pointer to the system. */
System *system;
- /** Pointer to physical memory. */
- PhysicalMemory *physmem;
-#endif
-
- /** Event to call process() on once draining has completed. */
- Event *drainEvent;
-
- /** Counter of how many stages have completed draining. */
- int drainCount;
-
/** Pointers to all of the threads in the CPU. */
std::vector<Thread *> thread;
- /** Whether or not the CPU should defer its registration. */
- bool deferRegistration;
-
- /** Is there a context switch pending? */
- bool contextSwitch;
-
/** Threads Scheduled to Enter CPU */
std::list<int> cpuWaitList;
/** The cycle that the CPU was last running, used for statistics. */
- Tick lastRunningCycle;
+ Cycles lastRunningCycle;
/** The cycle that the CPU was last activated by a new thread*/
Tick lastActivatedCycle;
- /** Number of Threads CPU can process */
- unsigned numThreads;
-
/** Mapping for system thread id to cpu id */
- std::map<unsigned,unsigned> threadMap;
+ std::map<ThreadID, unsigned> threadMap;
/** Available thread ids in the cpu*/
- std::vector<unsigned> tids;
+ std::vector<ThreadID> tids;
/** CPU read function, forwards read to LSQ. */
- template <class T>
- Fault read(RequestPtr &req, T &data, int load_idx)
+ Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
+ int load_idx)
{
- return this->iew.ldstQueue.read(req, data, load_idx);
+ return this->iew.ldstQueue.read(req, sreqLow, sreqHigh, load_idx);
}
/** CPU write function, forwards write to LSQ. */
- template <class T>
- Fault write(RequestPtr &req, T &data, int store_idx)
+ Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
+ uint8_t *data, int store_idx)
{
- return this->iew.ldstQueue.write(req, data, store_idx);
+ return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
+ data, store_idx);
}
- Addr lockAddr;
+ /** Used by the fetch unit to get a hold of the instruction port. */
+ MasterPort &getInstPort() override { return icachePort; }
- /** Temporary fix for the lock flag, works in the UP case. */
- bool lockFlag;
+ /** Get the dcache port (used to find block size for translations). */
+ MasterPort &getDataPort() override { return dcachePort; }
/** Stat for total number of times the CPU is descheduled. */
Stats::Scalar timesIdled;
/** Stat for total number of cycles the CPU spends descheduled. */
Stats::Scalar idleCycles;
+ /** Stat for total number of cycles the CPU spends descheduled due to a
+ * quiesce operation or waiting for an interrupt. */
+ Stats::Scalar quiesceCycles;
/** Stat for the number of committed instructions per thread. */
Stats::Vector committedInsts;
- /** Stat for the total number of committed instructions. */
- Stats::Scalar totalCommittedInsts;
+ /** Stat for the number of committed ops (including micro ops) per thread. */
+ Stats::Vector committedOps;
/** Stat for the CPI per thread. */
Stats::Formula cpi;
/** Stat for the total CPI. */
Stats::Formula ipc;
/** Stat for the total IPC. */
Stats::Formula totalIpc;
+
+ //number of integer register file accesses
+ Stats::Scalar intRegfileReads;
+ Stats::Scalar intRegfileWrites;
+ //number of float register file accesses
+ Stats::Scalar fpRegfileReads;
+ Stats::Scalar fpRegfileWrites;
+ //number of CC register file accesses
+ Stats::Scalar ccRegfileReads;
+ Stats::Scalar ccRegfileWrites;
+ //number of misc
+ Stats::Scalar miscRegfileReads;
+ Stats::Scalar miscRegfileWrites;
};
#endif // __CPU_O3_CPU_HH__
projects / gem5.git / blobdiff