#include "arch/types.hh"
#include "base/statistics.hh"
-#include "base/timebuf.hh"
+#include "cpu/timebuf.hh"
#include "config/full_system.hh"
+#include "config/the_isa.hh"
#include "config/use_checker.hh"
#include "cpu/activity.hh"
#include "cpu/base.hh"
SwitchedOut
};
- TheISA::ITB * itb;
- TheISA::DTB * dtb;
+ TheISA::TLB * itb;
+ TheISA::TLB * dtb;
/** Overall CPU status. */
Status _status;
void scheduleTickEvent(int delay)
{
if (tickEvent.squashed())
- reschedule(tickEvent, nextCycle(curTick + ticks(delay)));
+ reschedule(tickEvent, nextCycle(curTick() + ticks(delay)));
else if (!tickEvent.scheduled())
- schedule(tickEvent, nextCycle(curTick + ticks(delay)));
+ schedule(tickEvent, nextCycle(curTick() + ticks(delay)));
}
/** Unschedule tick event, regardless of its current state. */
{
private:
/** Number of Thread to Activate */
- int tid;
+ ThreadID tid;
/** Pointer to the CPU. */
FullO3CPU<Impl> *cpu;
};
/** Schedule thread to activate , regardless of its current state. */
- void scheduleActivateThreadEvent(int tid, int delay)
+ void
+ scheduleActivateThreadEvent(ThreadID tid, int delay)
{
// Schedule thread to activate, regardless of its current state.
if (activateThreadEvent[tid].squashed())
reschedule(activateThreadEvent[tid],
- nextCycle(curTick + ticks(delay)));
+ nextCycle(curTick() + ticks(delay)));
else if (!activateThreadEvent[tid].scheduled())
schedule(activateThreadEvent[tid],
- nextCycle(curTick + ticks(delay)));
+ nextCycle(curTick() + ticks(delay)));
}
/** Unschedule actiavte thread event, regardless of its current state. */
- void unscheduleActivateThreadEvent(int tid)
+ void
+ unscheduleActivateThreadEvent(ThreadID tid)
{
if (activateThreadEvent[tid].scheduled())
activateThreadEvent[tid].squash();
}
-#if !FULL_SYSTEM
- TheISA::IntReg getSyscallArg(int i, int tid);
-
- /** Used to shift args for indirect syscall. */
- void setSyscallArg(int i, TheISA::IntReg val, int tid);
-#endif
-
/** The tick event used for scheduling CPU ticks. */
ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
{
private:
/** Number of Thread to deactivate */
- int tid;
+ ThreadID tid;
/** Should the thread be removed from the CPU? */
bool remove;
};
/** Schedule cpu to deallocate thread context.*/
- void scheduleDeallocateContextEvent(int tid, bool remove, int delay)
+ void
+ scheduleDeallocateContextEvent(ThreadID tid, bool remove, int delay)
{
// Schedule thread to activate, regardless of its current state.
if (deallocateContextEvent[tid].squashed())
reschedule(deallocateContextEvent[tid],
- nextCycle(curTick + ticks(delay)));
+ nextCycle(curTick() + ticks(delay)));
else if (!deallocateContextEvent[tid].scheduled())
schedule(deallocateContextEvent[tid],
- nextCycle(curTick + ticks(delay)));
+ nextCycle(curTick() + ticks(delay)));
}
/** Unschedule thread deallocation in CPU */
- void unscheduleDeallocateContextEvent(int tid)
+ void
+ unscheduleDeallocateContextEvent(ThreadID tid)
{
if (deallocateContextEvent[tid].scheduled())
deallocateContextEvent[tid].squash();
{ return activeThreads.size(); }
/** Add Thread to Active Threads List */
- void activateThread(unsigned tid);
+ void activateThread(ThreadID tid);
/** Remove Thread from Active Threads List */
- void deactivateThread(unsigned tid);
+ void deactivateThread(ThreadID tid);
/** Setup CPU to insert a thread's context */
- void insertThread(unsigned tid);
+ void insertThread(ThreadID tid);
/** Remove all of a thread's context from CPU */
- void removeThread(unsigned tid);
+ void removeThread(ThreadID tid);
/** Count the Total Instructions Committed in the CPU. */
- virtual Counter totalInstructions() const
- {
- Counter total(0);
-
- for (int i=0; i < thread.size(); i++)
- total += thread[i]->numInst;
-
- return total;
- }
+ virtual Counter totalInstructions() const;
/** Add Thread to Active Threads List. */
- void activateContext(int tid, int delay);
+ void activateContext(ThreadID tid, int delay);
/** Remove Thread from Active Threads List */
- void suspendContext(int tid);
+ void suspendContext(ThreadID tid);
/** Remove Thread from Active Threads List &&
* Possibly Remove Thread Context from CPU.
*/
- bool deallocateContext(int tid, bool remove, int delay = 1);
+ bool deallocateContext(ThreadID tid, bool remove, int delay = 1);
/** Remove Thread from Active Threads List &&
* Remove Thread Context from CPU.
*/
- void haltContext(int tid);
+ void haltContext(ThreadID tid);
/** Activate a Thread When CPU Resources are Available. */
- void activateWhenReady(int tid);
+ void activateWhenReady(ThreadID tid);
/** Add or Remove a Thread Context in the CPU. */
void doContextSwitch();
/** Executes a syscall.
* @todo: Determine if this needs to be virtual.
*/
- void syscall(int64_t callnum, int tid);
-
- /** Sets the return value of a syscall. */
- void setSyscallReturn(SyscallReturn return_value, int tid);
-
+ void syscall(int64_t callnum, ThreadID tid);
#endif
/** Starts draining the CPU's pipeline of all instructions in
{ return globalSeqNum++; }
/** Traps to handle given fault. */
- void trap(Fault fault, unsigned tid);
+ void trap(Fault fault, ThreadID tid, StaticInstPtr inst);
#if FULL_SYSTEM
/** HW return from error interrupt. */
- Fault hwrei(unsigned tid);
+ Fault hwrei(ThreadID tid);
- bool simPalCheck(int palFunc, unsigned tid);
+ bool simPalCheck(int palFunc, ThreadID tid);
/** Returns the Fault for any valid interrupt. */
Fault getInterrupts();
/** Check if this address is a valid data address. */
bool validDataAddr(Addr addr) { return true; }
-
- /** Get instruction asid. */
- int getInstAsid(unsigned tid)
- { return regFile.miscRegs[tid].getInstAsid(); }
-
- /** Get data asid. */
- int getDataAsid(unsigned tid)
- { return regFile.miscRegs[tid].getDataAsid(); }
-#else
- /** Get instruction asid. */
- int getInstAsid(unsigned tid)
- { return thread[tid]->getInstAsid(); }
-
- /** Get data asid. */
- int getDataAsid(unsigned tid)
- { return thread[tid]->getDataAsid(); }
-
#endif
/** Register accessors. Index refers to the physical register index. */
/** Reads a miscellaneous register. */
- TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid);
+ TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid);
/** Reads a misc. register, including any side effects the read
* might have as defined by the architecture.
*/
- TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
+ TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
/** Sets a miscellaneous register. */
- void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, unsigned tid);
+ void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
+ ThreadID tid);
/** Sets a misc. register, including any side effects the write
* might have as defined by the architecture.
*/
void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
- unsigned tid);
+ ThreadID tid);
uint64_t readIntReg(int reg_idx);
TheISA::FloatReg readFloatReg(int reg_idx);
- TheISA::FloatReg readFloatReg(int reg_idx, int width);
-
TheISA::FloatRegBits readFloatRegBits(int reg_idx);
- TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width);
-
void setIntReg(int reg_idx, uint64_t val);
void setFloatReg(int reg_idx, TheISA::FloatReg val);
- void setFloatReg(int reg_idx, TheISA::FloatReg val, int width);
-
void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
- void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width);
-
- uint64_t readArchIntReg(int reg_idx, unsigned tid);
+ uint64_t readArchIntReg(int reg_idx, ThreadID tid);
- float readArchFloatRegSingle(int reg_idx, unsigned tid);
+ float readArchFloatReg(int reg_idx, ThreadID tid);
- double readArchFloatRegDouble(int reg_idx, unsigned tid);
-
- uint64_t readArchFloatRegInt(int reg_idx, unsigned tid);
+ uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
/** Architectural register accessors. Looks up in the commit
* rename table to obtain the true physical index of the
* architected register first, then accesses that physical
* register.
*/
- void setArchIntReg(int reg_idx, uint64_t val, unsigned tid);
+ void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
- void setArchFloatRegSingle(int reg_idx, float val, unsigned tid);
+ void setArchFloatReg(int reg_idx, float val, ThreadID tid);
- void setArchFloatRegDouble(int reg_idx, double val, unsigned tid);
+ void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
- void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid);
+ /** Sets the commit PC state of a specific thread. */
+ void pcState(const TheISA::PCState &newPCState, ThreadID tid);
- /** Reads the commit PC of a specific thread. */
- Addr readPC(unsigned tid);
+ /** Reads the commit PC state of a specific thread. */
+ TheISA::PCState pcState(ThreadID tid);
- /** Sets the commit PC of a specific thread. */
- void setPC(Addr new_PC, unsigned tid);
+ /** Reads the commit PC of a specific thread. */
+ Addr instAddr(ThreadID tid);
/** Reads the commit micro PC of a specific thread. */
- Addr readMicroPC(unsigned tid);
-
- /** Sets the commmit micro PC of a specific thread. */
- void setMicroPC(Addr new_microPC, unsigned tid);
+ MicroPC microPC(ThreadID tid);
/** Reads the next PC of a specific thread. */
- Addr readNextPC(unsigned tid);
-
- /** Sets the next PC of a specific thread. */
- void setNextPC(Addr val, unsigned tid);
-
- /** Reads the next NPC of a specific thread. */
- Addr readNextNPC(unsigned tid);
-
- /** Sets the next NPC of a specific thread. */
- void setNextNPC(Addr val, unsigned tid);
-
- /** Reads the commit next micro PC of a specific thread. */
- Addr readNextMicroPC(unsigned tid);
-
- /** Sets the commit next micro PC of a specific thread. */
- void setNextMicroPC(Addr val, unsigned tid);
+ Addr nextInstAddr(ThreadID tid);
/** Initiates a squash of all in-flight instructions for a given
* thread. The source of the squash is an external update of
* state through the TC.
*/
- void squashFromTC(unsigned tid);
+ void squashFromTC(ThreadID tid);
/** Function to add instruction onto the head of the list of the
* instructions. Used when new instructions are fetched.
ListIt addInst(DynInstPtr &inst);
/** Function to tell the CPU that an instruction has completed. */
- void instDone(unsigned tid);
+ void instDone(ThreadID tid);
/** Add Instructions to the CPU Remove List*/
void addToRemoveList(DynInstPtr &inst);
/** Remove all instructions that are not currently in the ROB.
* There's also an option to not squash delay slot instructions.*/
- void removeInstsNotInROB(unsigned tid);
+ void removeInstsNotInROB(ThreadID tid);
/** Remove all instructions younger than the given sequence number. */
- void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);
+ void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
/** Removes the instruction pointed to by the iterator. */
- inline void squashInstIt(const ListIt &instIt, const unsigned &tid);
+ inline void squashInstIt(const ListIt &instIt, ThreadID tid);
/** Cleans up all instructions on the remove list. */
void cleanUpRemovedInsts();
typename CPUPolicy::ROB rob;
/** Active Threads List */
- std::list<unsigned> activeThreads;
+ std::list<ThreadID> activeThreads;
/** Integer Register Scoreboard */
Scoreboard scoreboard;
+ TheISA::ISA isa[Impl::MaxThreads];
+
public:
/** Enum to give each stage a specific index, so when calling
* activateStage() or deactivateStage(), they can specify which stage
#endif
/** Gets a free thread id. Use if thread ids change across system. */
- int getFreeTid();
+ ThreadID getFreeTid();
public:
/** Returns a pointer to a thread context. */
- ThreadContext *tcBase(unsigned tid)
+ ThreadContext *
+ tcBase(ThreadID tid)
{
return thread[tid]->getTC();
}
#if FULL_SYSTEM
/** Pointer to the system. */
System *system;
-
- /** Pointer to physical memory. */
- PhysicalMemory *physmem;
#endif
/** Event to call process() on once draining has completed. */
/** The cycle that the CPU was last activated by a new thread*/
Tick lastActivatedCycle;
- /** Number of Threads CPU can process */
- unsigned numThreads;
-
/** Mapping for system thread id to cpu id */
- std::map<unsigned,unsigned> threadMap;
+ std::map<ThreadID, unsigned> threadMap;
/** Available thread ids in the cpu*/
- std::vector<unsigned> tids;
+ std::vector<ThreadID> tids;
/** CPU read function, forwards read to LSQ. */
- template <class T>
- Fault read(RequestPtr &req, T &data, int load_idx)
+ Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
+ uint8_t *data, int load_idx)
{
- return this->iew.ldstQueue.read(req, data, load_idx);
+ return this->iew.ldstQueue.read(req, sreqLow, sreqHigh,
+ data, load_idx);
}
/** CPU write function, forwards write to LSQ. */
- template <class T>
- Fault write(RequestPtr &req, T &data, int store_idx)
+ Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
+ uint8_t *data, int store_idx)
{
- return this->iew.ldstQueue.write(req, data, store_idx);
+ return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
+ data, store_idx);
}
+ /** Get the dcache port (used to find block size for translations). */
+ Port *getDcachePort() { return this->iew.ldstQueue.getDcachePort(); }
+
Addr lockAddr;
/** Temporary fix for the lock flag, works in the UP case. */
bool lockFlag;
/** Stat for total number of times the CPU is descheduled. */
- Stats::Scalar<> timesIdled;
+ Stats::Scalar timesIdled;
/** Stat for total number of cycles the CPU spends descheduled. */
- Stats::Scalar<> idleCycles;
+ Stats::Scalar idleCycles;
/** Stat for the number of committed instructions per thread. */
- Stats::Vector<> committedInsts;
+ Stats::Vector committedInsts;
/** Stat for the total number of committed instructions. */
- Stats::Scalar<> totalCommittedInsts;
+ Stats::Scalar totalCommittedInsts;
/** Stat for the CPI per thread. */
Stats::Formula cpi;
/** Stat for the total CPI. */
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