/*
+ * Copyright (c) 2011-2013, 2016-2019 ARM Limited
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2004-2005 The Regents of The University of Michigan
* Copyright (c) 2011 Regents of the University of California
* All rights reserved.
#include <set>
#include <vector>
+#include "arch/generic/types.hh"
#include "arch/types.hh"
#include "base/statistics.hh"
#include "config/the_isa.hh"
-#include "config/use_checker.hh"
#include "cpu/o3/comm.hh"
#include "cpu/o3/cpu_policy.hh"
#include "cpu/o3/scoreboard.hh"
class MemObject;
class Process;
-class BaseCPUParams;
+struct BaseCPUParams;
class BaseO3CPU : public BaseCPU
{
typedef typename Impl::DynInstPtr DynInstPtr;
typedef typename Impl::O3CPU O3CPU;
+ using VecElem = TheISA::VecElem;
+ using VecRegContainer = TheISA::VecRegContainer;
+
+ using VecPredRegContainer = TheISA::VecPredRegContainer;
+
typedef O3ThreadState<Impl> ImplState;
typedef O3ThreadState<Impl> Thread;
SwitchedOut
};
- TheISA::TLB * itb;
- TheISA::TLB * dtb;
+ BaseTLB *itb;
+ BaseTLB *dtb;
+ using LSQRequest = typename LSQ<Impl>::LSQRequest;
/** Overall CPU status. */
Status _status;
- /** Per-thread status in CPU, used for SMT. */
- Status _threadStatus[Impl::MaxThreads];
-
private:
- class TickEvent : public Event
- {
- private:
- /** Pointer to the CPU. */
- FullO3CPU<Impl> *cpu;
-
- public:
- /** Constructs a tick event. */
- TickEvent(FullO3CPU<Impl> *c);
- /** Processes a tick event, calling tick() on the CPU. */
- void process();
- /** Returns the description of the tick event. */
- const char *description() const;
- };
-
- /** The tick event used for scheduling CPU ticks. */
- TickEvent tickEvent;
-
- /** Schedule tick event, regardless of its current state. */
- void scheduleTickEvent(int delay)
- {
- if (tickEvent.squashed())
- reschedule(tickEvent, nextCycle(curTick() + ticks(delay)));
- else if (!tickEvent.scheduled())
- schedule(tickEvent, nextCycle(curTick() + ticks(delay)));
- }
-
- /** Unschedule tick event, regardless of its current state. */
- void unscheduleTickEvent()
- {
- if (tickEvent.scheduled())
- tickEvent.squash();
- }
-
- class ActivateThreadEvent : public Event
+ /**
+ * IcachePort class for instruction fetch.
+ */
+ class IcachePort : public MasterPort
{
- private:
- /** Number of Thread to Activate */
- ThreadID tid;
-
- /** Pointer to the CPU. */
- FullO3CPU<Impl> *cpu;
+ protected:
+ /** Pointer to fetch. */
+ DefaultFetch<Impl> *fetch;
public:
- /** Constructs the event. */
- ActivateThreadEvent();
+ /** Default constructor. */
+ IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
+ : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
+ { }
- /** Initialize Event */
- void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
+ protected:
- /** Processes the event, calling activateThread() on the CPU. */
- void process();
+ /** Timing version of receive. Handles setting fetch to the
+ * proper status to start fetching. */
+ virtual bool recvTimingResp(PacketPtr pkt);
- /** Returns the description of the event. */
- const char *description() const;
+ /** Handles doing a retry of a failed fetch. */
+ virtual void recvReqRetry();
};
- /** Schedule thread to activate , regardless of its current state. */
- void
- scheduleActivateThreadEvent(ThreadID tid, int delay)
- {
- // Schedule thread to activate, regardless of its current state.
- if (activateThreadEvent[tid].squashed())
- reschedule(activateThreadEvent[tid],
- nextCycle(curTick() + ticks(delay)));
- else if (!activateThreadEvent[tid].scheduled()) {
- Tick when = nextCycle(curTick() + ticks(delay));
-
- // Check if the deallocateEvent is also scheduled, and make
- // sure they do not happen at same time causing a sleep that
- // is never woken from.
- if (deallocateContextEvent[tid].scheduled() &&
- deallocateContextEvent[tid].when() == when) {
- when++;
- }
-
- schedule(activateThreadEvent[tid], when);
- }
- }
-
- /** Unschedule actiavte thread event, regardless of its current state. */
- void
- unscheduleActivateThreadEvent(ThreadID tid)
- {
- if (activateThreadEvent[tid].scheduled())
- activateThreadEvent[tid].squash();
- }
-
- /** The tick event used for scheduling CPU ticks. */
- ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
-
- class DeallocateContextEvent : public Event
+ /**
+ * DcachePort class for the load/store queue.
+ */
+ class DcachePort : public MasterPort
{
- private:
- /** Number of Thread to deactivate */
- ThreadID tid;
-
- /** Should the thread be removed from the CPU? */
- bool remove;
+ protected:
- /** Pointer to the CPU. */
+ /** Pointer to LSQ. */
+ LSQ<Impl> *lsq;
FullO3CPU<Impl> *cpu;
public:
- /** Constructs the event. */
- DeallocateContextEvent();
+ /** Default constructor. */
+ DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
+ : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq),
+ cpu(_cpu)
+ { }
+
+ protected:
+
+ /** Timing version of receive. Handles writing back and
+ * completing the load or store that has returned from
+ * memory. */
+ virtual bool recvTimingResp(PacketPtr pkt);
+ virtual void recvTimingSnoopReq(PacketPtr pkt);
+
+ virtual void recvFunctionalSnoop(PacketPtr pkt)
+ {
+ // @todo: Is there a need for potential invalidation here?
+ }
- /** Initialize Event */
- void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
+ /** Handles doing a retry of the previous send. */
+ virtual void recvReqRetry();
- /** Processes the event, calling activateThread() on the CPU. */
- void process();
+ /**
+ * As this CPU requires snooping to maintain the load store queue
+ * change the behaviour from the base CPU port.
+ *
+ * @return true since we have to snoop
+ */
+ virtual bool isSnooping() const { return true; }
+ };
- /** Sets whether the thread should also be removed from the CPU. */
- void setRemove(bool _remove) { remove = _remove; }
+ /** The tick event used for scheduling CPU ticks. */
+ EventFunctionWrapper tickEvent;
- /** Returns the description of the event. */
- const char *description() const;
- };
+ /** The exit event used for terminating all ready-to-exit threads */
+ EventFunctionWrapper threadExitEvent;
- /** Schedule cpu to deallocate thread context.*/
- void
- scheduleDeallocateContextEvent(ThreadID tid, bool remove, int delay)
+ /** Schedule tick event, regardless of its current state. */
+ void scheduleTickEvent(Cycles delay)
{
- // Schedule thread to activate, regardless of its current state.
- if (deallocateContextEvent[tid].squashed())
- reschedule(deallocateContextEvent[tid],
- nextCycle(curTick() + ticks(delay)));
- else if (!deallocateContextEvent[tid].scheduled())
- schedule(deallocateContextEvent[tid],
- nextCycle(curTick() + ticks(delay)));
+ if (tickEvent.squashed())
+ reschedule(tickEvent, clockEdge(delay));
+ else if (!tickEvent.scheduled())
+ schedule(tickEvent, clockEdge(delay));
}
- /** Unschedule thread deallocation in CPU */
- void
- unscheduleDeallocateContextEvent(ThreadID tid)
+ /** Unschedule tick event, regardless of its current state. */
+ void unscheduleTickEvent()
{
- if (deallocateContextEvent[tid].scheduled())
- deallocateContextEvent[tid].squash();
+ if (tickEvent.scheduled())
+ tickEvent.squash();
}
- /** The tick event used for scheduling CPU ticks. */
- DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
+ /**
+ * Check if the pipeline has drained and signal drain done.
+ *
+ * This method checks if a drain has been requested and if the CPU
+ * has drained successfully (i.e., there are no instructions in
+ * the pipeline). If the CPU has drained, it deschedules the tick
+ * event and signals the drain manager.
+ *
+ * @return False if a drain hasn't been requested or the CPU
+ * hasn't drained, true otherwise.
+ */
+ bool tryDrain();
+
+ /**
+ * Perform sanity checks after a drain.
+ *
+ * This method is called from drain() when it has determined that
+ * the CPU is fully drained when gem5 is compiled with the NDEBUG
+ * macro undefined. The intention of this method is to do more
+ * extensive tests than the isDrained() method to weed out any
+ * draining bugs.
+ */
+ void drainSanityCheck() const;
+
+ /** Check if a system is in a drained state. */
+ bool isDrained() const;
public:
/** Constructs a CPU with the given parameters. */
~FullO3CPU();
/** Registers statistics. */
- void regStats();
+ void regStats() override;
+
+ ProbePointArg<PacketPtr> *ppInstAccessComplete;
+ ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete;
+
+ /** Register probe points. */
+ void regProbePoints() override;
void demapPage(Addr vaddr, uint64_t asn)
{
this->dtb->demapPage(vaddr, asn);
}
- /** Returns a specific port. */
- Port *getPort(const std::string &if_name, int idx);
-
/** Ticks CPU, calling tick() on each stage, and checking the overall
* activity to see if the CPU should deschedule itself.
*/
void tick();
/** Initialize the CPU */
- void init();
+ void init() override;
+
+ void startup() override;
/** Returns the Number of Active Threads in the CPU */
int numActiveThreads()
void removeThread(ThreadID tid);
/** Count the Total Instructions Committed in the CPU. */
- virtual Counter totalInstructions() const;
+ Counter totalInsts() const override;
+
+ /** Count the Total Ops (including micro ops) committed in the CPU. */
+ Counter totalOps() const override;
/** Add Thread to Active Threads List. */
- void activateContext(ThreadID tid, int delay);
+ void activateContext(ThreadID tid) override;
/** Remove Thread from Active Threads List */
- void suspendContext(ThreadID tid);
-
- /** Remove Thread from Active Threads List &&
- * Possibly Remove Thread Context from CPU.
- */
- bool deallocateContext(ThreadID tid, bool remove, int delay = 1);
+ void suspendContext(ThreadID tid) override;
/** Remove Thread from Active Threads List &&
* Remove Thread Context from CPU.
*/
- void haltContext(ThreadID tid);
-
- /** Activate a Thread When CPU Resources are Available. */
- void activateWhenReady(ThreadID tid);
-
- /** Add or Remove a Thread Context in the CPU. */
- void doContextSwitch();
+ void haltContext(ThreadID tid) override;
/** Update The Order In Which We Process Threads. */
void updateThreadPriority();
- /** Serialize state. */
- virtual void serialize(std::ostream &os);
+ /** Is the CPU draining? */
+ bool isDraining() const { return drainState() == DrainState::Draining; }
+
+ void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
+ void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
+
+ /** Insert tid to the list of threads trying to exit */
+ void addThreadToExitingList(ThreadID tid);
- /** Unserialize from a checkpoint. */
- virtual void unserialize(Checkpoint *cp, const std::string §ion);
+ /** Is the thread trying to exit? */
+ bool isThreadExiting(ThreadID tid) const;
+
+ /**
+ * If a thread is trying to exit and its corresponding trap event
+ * has been completed, schedule an event to terminate the thread.
+ */
+ void scheduleThreadExitEvent(ThreadID tid);
+
+ /** Terminate all threads that are ready to exit */
+ void exitThreads();
public:
/** Executes a syscall.
* @todo: Determine if this needs to be virtual.
*/
- void syscall(int64_t callnum, ThreadID tid);
+ void syscall(int64_t callnum, ThreadID tid, Fault *fault);
/** Starts draining the CPU's pipeline of all instructions in
* order to stop all memory accesses. */
- virtual unsigned int drain(Event *drain_event);
+ DrainState drain() override;
/** Resumes execution after a drain. */
- virtual void resume();
-
- /** Signals to this CPU that a stage has completed switching out. */
- void signalDrained();
+ void drainResume() override;
+
+ /**
+ * Commit has reached a safe point to drain a thread.
+ *
+ * Commit calls this method to inform the pipeline that it has
+ * reached a point where it is not executed microcode and is about
+ * to squash uncommitted instructions to fully drain the pipeline.
+ */
+ void commitDrained(ThreadID tid);
/** Switches out this CPU. */
- virtual void switchOut();
+ void switchOut() override;
/** Takes over from another CPU. */
- virtual void takeOverFrom(BaseCPU *oldCPU);
+ void takeOverFrom(BaseCPU *oldCPU) override;
+
+ void verifyMemoryMode() const override;
/** Get the current instruction sequence number, and increment it. */
InstSeqNum getAndIncrementInstSeq()
{ return globalSeqNum++; }
/** Traps to handle given fault. */
- void trap(Fault fault, ThreadID tid, StaticInstPtr inst);
+ void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst);
/** HW return from error interrupt. */
Fault hwrei(ThreadID tid);
bool simPalCheck(int palFunc, ThreadID tid);
+ /** Check if a change in renaming is needed for vector registers.
+ * The vecMode variable is updated and propagated to rename maps.
+ *
+ * @param tid ThreadID
+ * @param freelist list of free registers
+ */
+ void switchRenameMode(ThreadID tid, UnifiedFreeList* freelist);
+
/** Returns the Fault for any valid interrupt. */
Fault getInterrupts();
/** Processes any an interrupt fault. */
- void processInterrupts(Fault interrupt);
+ void processInterrupts(const Fault &interrupt);
/** Halts the CPU. */
void halt() { panic("Halt not implemented!\n"); }
- /** Update the Virt and Phys ports of all ThreadContexts to
- * reflect change in memory connections. */
- void updateMemPorts();
-
- /** Check if this address is a valid instruction address. */
- bool validInstAddr(Addr addr) { return true; }
-
- /** Check if this address is a valid data address. */
- bool validDataAddr(Addr addr) { return true; }
-
/** Register accessors. Index refers to the physical register index. */
/** Reads a miscellaneous register. */
- TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid);
+ RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const;
/** Reads a misc. register, including any side effects the read
* might have as defined by the architecture.
*/
- TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
+ RegVal readMiscReg(int misc_reg, ThreadID tid);
/** Sets a miscellaneous register. */
- void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
- ThreadID tid);
+ void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid);
/** Sets a misc. register, including any side effects the write
* might have as defined by the architecture.
*/
- void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
- ThreadID tid);
+ void setMiscReg(int misc_reg, RegVal val, ThreadID tid);
+
+ RegVal readIntReg(PhysRegIdPtr phys_reg);
+
+ RegVal readFloatReg(PhysRegIdPtr phys_reg);
+
+ const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const;
+
+ /**
+ * Read physical vector register for modification.
+ */
+ VecRegContainer& getWritableVecReg(PhysRegIdPtr reg_idx);
+
+ /** Returns current vector renaming mode */
+ Enums::VecRegRenameMode vecRenameMode() const { return vecMode; }
+
+ /** Sets the current vector renaming mode */
+ void vecRenameMode(Enums::VecRegRenameMode vec_mode)
+ { vecMode = vec_mode; }
+
+ /**
+ * Read physical vector register lane
+ */
+ template<typename VecElem, int LaneIdx>
+ VecLaneT<VecElem, true>
+ readVecLane(PhysRegIdPtr phys_reg) const
+ {
+ vecRegfileReads++;
+ return regFile.readVecLane<VecElem, LaneIdx>(phys_reg);
+ }
+
+ /**
+ * Read physical vector register lane
+ */
+ template<typename VecElem>
+ VecLaneT<VecElem, true>
+ readVecLane(PhysRegIdPtr phys_reg) const
+ {
+ vecRegfileReads++;
+ return regFile.readVecLane<VecElem>(phys_reg);
+ }
+
+ /** Write a lane of the destination vector register. */
+ template<typename LD>
+ void
+ setVecLane(PhysRegIdPtr phys_reg, const LD& val)
+ {
+ vecRegfileWrites++;
+ return regFile.setVecLane(phys_reg, val);
+ }
+
+ const VecElem& readVecElem(PhysRegIdPtr reg_idx) const;
- uint64_t readIntReg(int reg_idx);
+ const VecPredRegContainer& readVecPredReg(PhysRegIdPtr reg_idx) const;
- TheISA::FloatReg readFloatReg(int reg_idx);
+ VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr reg_idx);
- TheISA::FloatRegBits readFloatRegBits(int reg_idx);
+ RegVal readCCReg(PhysRegIdPtr phys_reg);
- void setIntReg(int reg_idx, uint64_t val);
+ void setIntReg(PhysRegIdPtr phys_reg, RegVal val);
- void setFloatReg(int reg_idx, TheISA::FloatReg val);
+ void setFloatReg(PhysRegIdPtr phys_reg, RegVal val);
- void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
+ void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val);
- uint64_t readArchIntReg(int reg_idx, ThreadID tid);
+ void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val);
- float readArchFloatReg(int reg_idx, ThreadID tid);
+ void setVecPredReg(PhysRegIdPtr reg_idx, const VecPredRegContainer& val);
- uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
+ void setCCReg(PhysRegIdPtr phys_reg, RegVal val);
+
+ RegVal readArchIntReg(int reg_idx, ThreadID tid);
+
+ RegVal readArchFloatReg(int reg_idx, ThreadID tid);
+
+ const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const;
+ /** Read architectural vector register for modification. */
+ VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID tid);
+
+ /** Read architectural vector register lane. */
+ template<typename VecElem>
+ VecLaneT<VecElem, true>
+ readArchVecLane(int reg_idx, int lId, ThreadID tid) const
+ {
+ PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
+ RegId(VecRegClass, reg_idx));
+ return readVecLane<VecElem>(phys_reg);
+ }
+
+
+ /** Write a lane of the destination vector register. */
+ template<typename LD>
+ void
+ setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD& val)
+ {
+ PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
+ RegId(VecRegClass, reg_idx));
+ setVecLane(phys_reg, val);
+ }
+
+ const VecElem& readArchVecElem(const RegIndex& reg_idx,
+ const ElemIndex& ldx, ThreadID tid) const;
+
+ const VecPredRegContainer& readArchVecPredReg(int reg_idx,
+ ThreadID tid) const;
+
+ VecPredRegContainer& getWritableArchVecPredReg(int reg_idx, ThreadID tid);
+
+ RegVal readArchCCReg(int reg_idx, ThreadID tid);
/** Architectural register accessors. Looks up in the commit
* rename table to obtain the true physical index of the
* architected register first, then accesses that physical
* register.
*/
- void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
+ void setArchIntReg(int reg_idx, RegVal val, ThreadID tid);
+
+ void setArchFloatReg(int reg_idx, RegVal val, ThreadID tid);
+
+ void setArchVecPredReg(int reg_idx, const VecPredRegContainer& val,
+ ThreadID tid);
- void setArchFloatReg(int reg_idx, float val, ThreadID tid);
+ void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid);
- void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
+ void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
+ const VecElem& val, ThreadID tid);
+
+ void setArchCCReg(int reg_idx, RegVal val, ThreadID tid);
/** Sets the commit PC state of a specific thread. */
void pcState(const TheISA::PCState &newPCState, ThreadID tid);
/** Function to add instruction onto the head of the list of the
* instructions. Used when new instructions are fetched.
*/
- ListIt addInst(DynInstPtr &inst);
+ ListIt addInst(const DynInstPtr &inst);
/** Function to tell the CPU that an instruction has completed. */
- void instDone(ThreadID tid);
+ void instDone(ThreadID tid, const DynInstPtr &inst);
/** Remove an instruction from the front end of the list. There's
* no restriction on location of the instruction.
*/
- void removeFrontInst(DynInstPtr &inst);
+ void removeFrontInst(const DynInstPtr &inst);
/** Remove all instructions that are not currently in the ROB.
* There's also an option to not squash delay slot instructions.*/
/** The commit stage. */
typename CPUPolicy::Commit commit;
+ /** The rename mode of the vector registers */
+ Enums::VecRegRenameMode vecMode;
+
/** The register file. */
- typename CPUPolicy::RegFile regFile;
+ PhysRegFile regFile;
/** The free list. */
typename CPUPolicy::FreeList freeList;
/** Active Threads List */
std::list<ThreadID> activeThreads;
+ /**
+ * This is a list of threads that are trying to exit. Each thread id
+ * is mapped to a boolean value denoting whether the thread is ready
+ * to exit.
+ */
+ std::unordered_map<ThreadID, bool> exitingThreads;
+
/** Integer Register Scoreboard */
Scoreboard scoreboard;
- TheISA::ISA isa[Impl::MaxThreads];
+ std::vector<TheISA::ISA *> isa;
+
+ /** Instruction port. Note that it has to appear after the fetch stage. */
+ IcachePort icachePort;
+
+ /** Data port. Note that it has to appear after the iew stages */
+ DcachePort dcachePort;
public:
/** Enum to give each stage a specific index, so when calling
/** Wakes the CPU, rescheduling the CPU if it's not already active. */
void wakeCPU();
- virtual void wakeup();
+ virtual void wakeup(ThreadID tid) override;
/** Gets a free thread id. Use if thread ids change across system. */
ThreadID getFreeTid();
/** The global sequence number counter. */
InstSeqNum globalSeqNum;//[Impl::MaxThreads];
-#if USE_CHECKER
/** Pointer to the checker, which can dynamically verify
* instruction results at run time. This can be set to NULL if it
* is not being used.
*/
- Checker<DynInstPtr> *checker;
-#endif
+ Checker<Impl> *checker;
/** Pointer to the system. */
System *system;
- /** Event to call process() on once draining has completed. */
- Event *drainEvent;
-
- /** Counter of how many stages have completed draining. */
- int drainCount;
-
/** Pointers to all of the threads in the CPU. */
std::vector<Thread *> thread;
- /** Whether or not the CPU should defer its registration. */
- bool deferRegistration;
-
- /** Is there a context switch pending? */
- bool contextSwitch;
-
/** Threads Scheduled to Enter CPU */
std::list<int> cpuWaitList;
/** The cycle that the CPU was last running, used for statistics. */
- Tick lastRunningCycle;
+ Cycles lastRunningCycle;
/** The cycle that the CPU was last activated by a new thread*/
Tick lastActivatedCycle;
/** Available thread ids in the cpu*/
std::vector<ThreadID> tids;
+ /** CPU pushRequest function, forwards request to LSQ. */
+ Fault pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
+ unsigned int size, Addr addr, Request::Flags flags,
+ uint64_t *res)
+ {
+ return iew.ldstQueue.pushRequest(inst, isLoad, data, size, addr,
+ flags, res);
+ }
+
/** CPU read function, forwards read to LSQ. */
- Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
- uint8_t *data, int load_idx)
+ Fault read(LSQRequest* req, int load_idx)
{
- return this->iew.ldstQueue.read(req, sreqLow, sreqHigh,
- data, load_idx);
+ return this->iew.ldstQueue.read(req, load_idx);
}
/** CPU write function, forwards write to LSQ. */
- Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
- uint8_t *data, int store_idx)
+ Fault write(LSQRequest* req, uint8_t *data, int store_idx)
{
- return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
- data, store_idx);
+ return this->iew.ldstQueue.write(req, data, store_idx);
}
- /** Get the dcache port (used to find block size for translations). */
- Port *getDcachePort() { return this->iew.ldstQueue.getDcachePort(); }
-
- Addr lockAddr;
+ /** Used by the fetch unit to get a hold of the instruction port. */
+ MasterPort &getInstPort() override { return icachePort; }
- /** Temporary fix for the lock flag, works in the UP case. */
- bool lockFlag;
+ /** Get the dcache port (used to find block size for translations). */
+ MasterPort &getDataPort() override { return dcachePort; }
/** Stat for total number of times the CPU is descheduled. */
Stats::Scalar timesIdled;
/** Stat for total number of cycles the CPU spends descheduled. */
Stats::Scalar idleCycles;
+ /** Stat for total number of cycles the CPU spends descheduled due to a
+ * quiesce operation or waiting for an interrupt. */
+ Stats::Scalar quiesceCycles;
/** Stat for the number of committed instructions per thread. */
Stats::Vector committedInsts;
- /** Stat for the total number of committed instructions. */
- Stats::Scalar totalCommittedInsts;
+ /** Stat for the number of committed ops (including micro ops) per thread. */
+ Stats::Vector committedOps;
/** Stat for the CPI per thread. */
Stats::Formula cpi;
/** Stat for the total CPI. */
//number of float register file accesses
Stats::Scalar fpRegfileReads;
Stats::Scalar fpRegfileWrites;
+ //number of vector register file accesses
+ mutable Stats::Scalar vecRegfileReads;
+ Stats::Scalar vecRegfileWrites;
+ //number of predicate register file accesses
+ mutable Stats::Scalar vecPredRegfileReads;
+ Stats::Scalar vecPredRegfileWrites;
+ //number of CC register file accesses
+ Stats::Scalar ccRegfileReads;
+ Stats::Scalar ccRegfileWrites;
//number of misc
Stats::Scalar miscRegfileReads;
Stats::Scalar miscRegfileWrites;
projects / gem5.git / blobdiff