{
private:
// Typedefs from the Impl.
- typedef typename Impl::FullCPU FullCPU;
+ typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::DynInstPtr DynInstPtr;
typedef typename Impl::Params Params;
typedef typename Impl::CPUPol CPUPol;
void regStats();
/** Sets CPU pointer. */
- void setCPU(FullCPU *cpu_ptr);
+ void setCPU(O3CPU *cpu_ptr);
/** Sets the main backwards communication time buffer pointer. */
void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
/** Sets pointer to list of active threads. */
void setActiveThreads(std::list<unsigned> *at_ptr);
+ /** Drains the decode stage. */
+ bool drain();
+
+ /** Resumes execution after a drain. */
+ void resume() { }
+
/** Switches out the decode stage. */
- void switchOut();
+ void switchOut() { }
/** Takes over from another CPU's thread. */
void takeOverFrom();
private:
// Interfaces to objects outside of decode.
/** CPU interface. */
- FullCPU *cpu;
+ O3CPU *cpu;
/** Time buffer interface. */
TimeBuffer<TimeStruct> *timeBuffer;
/** Maximum size of the skid buffer. */
unsigned skidBufferMax;
+ /** SeqNum of Squashing Branch Delay Instruction (used for MIPS)*/
+ Addr bdelayDoneSeqNum[Impl::MaxThreads];
+
+ /** Instruction used for squashing branch (used for MIPS)*/
+ DynInstPtr squashInst[Impl::MaxThreads];
+
+ /** Tells when their is a pending delay slot inst. to send
+ * to rename. If there is, then wait squash after the next
+ * instruction (used for MIPS).
+ */
+ bool squashAfterDelaySlot[Impl::MaxThreads];
+
+
/** Stat for total number of idle cycles. */
Stats::Scalar<> decodeIdleCycles;
/** Stat for total number of blocked cycles. */