O3: Remove some asserts that no longer seem to be valid.

[gem5.git] / src / cpu / o3 / decode_impl.hh

diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
index cee597716d1c43c82f120978b625533c36b1cd8f..a523a8b45129801f2c3455e03c463e7b47d247db 100644 (file)
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -34,6 +34,8 @@
 #include "config/the_isa.hh"
 #include "cpu/o3/decode.hh"
 #include "cpu/inst_seq.hh"
+#include "debug/Activity.hh"
+#include "debug/Decode.hh"
 #include "params/DerivO3CPU.hh"
 
 using namespace std;
@@ -75,44 +77,44 @@ void
 DefaultDecode<Impl>::regStats()
 {
     decodeIdleCycles
-        .name(name() + ".DECODE:IdleCycles")
+        .name(name() + ".IdleCycles")
         .desc("Number of cycles decode is idle")
         .prereq(decodeIdleCycles);
     decodeBlockedCycles
-        .name(name() + ".DECODE:BlockedCycles")
+        .name(name() + ".BlockedCycles")
         .desc("Number of cycles decode is blocked")
         .prereq(decodeBlockedCycles);
     decodeRunCycles
-        .name(name() + ".DECODE:RunCycles")
+        .name(name() + ".RunCycles")
         .desc("Number of cycles decode is running")
         .prereq(decodeRunCycles);
     decodeUnblockCycles
-        .name(name() + ".DECODE:UnblockCycles")
+        .name(name() + ".UnblockCycles")
         .desc("Number of cycles decode is unblocking")
         .prereq(decodeUnblockCycles);
     decodeSquashCycles
-        .name(name() + ".DECODE:SquashCycles")
+        .name(name() + ".SquashCycles")
         .desc("Number of cycles decode is squashing")
         .prereq(decodeSquashCycles);
     decodeBranchResolved
-        .name(name() + ".DECODE:BranchResolved")
+        .name(name() + ".BranchResolved")
         .desc("Number of times decode resolved a branch")
         .prereq(decodeBranchResolved);
     decodeBranchMispred
-        .name(name() + ".DECODE:BranchMispred")
+        .name(name() + ".BranchMispred")
         .desc("Number of times decode detected a branch misprediction")
         .prereq(decodeBranchMispred);
     decodeControlMispred
-        .name(name() + ".DECODE:ControlMispred")
+        .name(name() + ".ControlMispred")
         .desc("Number of times decode detected an instruction incorrectly"
               " predicted as a control")
         .prereq(decodeControlMispred);
     decodeDecodedInsts
-        .name(name() + ".DECODE:DecodedInsts")
+        .name(name() + ".DecodedInsts")
         .desc("Number of instructions handled by decode")
         .prereq(decodeDecodedInsts);
     decodeSquashedInsts
-        .name(name() + ".DECODE:SquashedInsts")
+        .name(name() + ".SquashedInsts")
         .desc("Number of squashed instructions handled by decode")
         .prereq(decodeSquashedInsts);
 }
@@ -278,6 +280,7 @@ DefaultDecode<Impl>::squash(DynInstPtr &inst, ThreadID tid)
     toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
     toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
     toFetch->decodeInfo[tid].branchTaken = inst->pcState().branching();
+    toFetch->decodeInfo[tid].squashInst = inst;
 
     InstSeqNum squash_seq_num = inst->seqNum;
 
@@ -444,10 +447,6 @@ void
 DefaultDecode<Impl>::sortInsts()
 {
     int insts_from_fetch = fromFetch->size;
-#ifdef DEBUG
-    for (ThreadID tid = 0; tid < numThreads; tid++)
-        assert(insts[tid].empty());
-#endif
     for (int i = 0; i < insts_from_fetch; ++i) {
         insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]);
     }
@@ -704,6 +703,10 @@ DefaultDecode<Impl>::decodeInsts(ThreadID tid)
         ++decodeDecodedInsts;
         --insts_available;
 
+#if TRACING_ON
+        inst->decodeTick = curTick();
+#endif
+
         // Ensure that if it was predicted as a branch, it really is a
         // branch.
         if (inst->readPredTaken() && !inst->isControl()) {