CPU: Eliminate the simPalCheck funciton.

[gem5.git] / src / cpu / o3 / fetch.hh

diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 280bf0e71b8baa94b2743fbda23a16136ed833e3..9886b667555afbcc760012fc63473e4de54f57e8 100644 (file)
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -33,13 +33,16 @@
 #define __CPU_O3_FETCH_HH__
 
 #include "arch/utility.hh"
+#include "arch/predecoder.hh"
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
 #include "cpu/pc_event.hh"
-#include "mem/packet_impl.hh"
+#include "mem/packet.hh"
 #include "mem/port.hh"
 #include "sim/eventq.hh"
 
+class DerivO3CPUParams;
+
 /**
  * DefaultFetch class handles both single threaded and SMT fetch. Its
  * width is specified by the parameters; each cycle it tries to fetch
@@ -57,7 +60,6 @@ class DefaultFetch
     typedef typename Impl::DynInst DynInst;
     typedef typename Impl::DynInstPtr DynInstPtr;
     typedef typename Impl::O3CPU O3CPU;
-    typedef typename Impl::Params Params;
 
     /** Typedefs from the CPU policy. */
     typedef typename CPUPol::BPredUnit BPredUnit;
@@ -80,9 +82,13 @@ class DefaultFetch
       public:
         /** Default constructor. */
         IcachePort(DefaultFetch<Impl> *_fetch)
-            : Port(_fetch->name() + "-iport"), fetch(_fetch)
+            : Port(_fetch->name() + "-iport", _fetch->cpu), fetch(_fetch)
         { }
 
+        bool snoopRangeSent;
+
+        virtual void setPeer(Port *port);
+
       protected:
         /** Atomic version of receive.  Panics. */
         virtual Tick recvAtomic(PacketPtr pkt);
@@ -95,8 +101,8 @@ class DefaultFetch
 
         /** Returns the address ranges of this device. */
         virtual void getDeviceAddressRanges(AddrRangeList &resp,
-                                            AddrRangeList &snoop)
-        { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,-1)); }
+                                            bool &snoop)
+        { resp.clear(); snoop = true; }
 
         /** Timing version of receive.  Handles setting fetch to the
          * proper status to start fetching. */
@@ -155,7 +161,7 @@ class DefaultFetch
 
   public:
     /** DefaultFetch constructor. */
-    DefaultFetch(Params *params);
+    DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params);
 
     /** Returns the name of fetch. */
     std::string name() const;
@@ -166,9 +172,6 @@ class DefaultFetch
     /** Returns the icache port. */
     Port *getIcachePort() { return icachePort; }
 
-    /** Sets CPU pointer. */
-    void setCPU(O3CPU *cpu_ptr);
-
     /** Sets the main backwards communication time buffer pointer. */
     void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
 
@@ -181,6 +184,9 @@ class DefaultFetch
     /** Initialize stage. */
     void initStage();
 
+    /** Tells the fetch stage that the Icache is set. */
+    void setIcache();
+
     /** Processes cache completion event. */
     void processCacheCompletion(PacketPtr pkt);
 
@@ -222,7 +228,7 @@ class DefaultFetch
      * @param next_NPC Used for ISAs which use delay slots.
      * @return Whether or not a branch was predicted as taken.
      */
-    bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC, Addr &next_NPC);
+    bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC, Addr &next_NPC, Addr &next_MicroPC);
 
     /**
      * Fetches the cache line that contains fetch_PC.  Returns any
@@ -237,13 +243,15 @@ class DefaultFetch
     bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid);
 
     /** Squashes a specific thread and resets the PC. */
-    inline void doSquash(const Addr &new_PC, unsigned tid);
+    inline void doSquash(const Addr &new_PC, const Addr &new_NPC,
+                         const Addr &new_MicroPC, unsigned tid);
 
     /** Squashes a specific thread and resets the PC. Also tells the CPU to
      * remove any instructions between fetch and decode that should be sqaushed.
      */
-    void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num,
-                          unsigned tid);
+    void squashFromDecode(const Addr &new_PC, const Addr &new_NPC,
+                          const Addr &new_MicroPC,
+                          const InstSeqNum &seq_num, unsigned tid);
 
     /** Checks if a thread is stalled. */
     bool checkStall(unsigned tid) const;
@@ -257,8 +265,9 @@ class DefaultFetch
      * remove any instructions that are not in the ROB. The source of this
      * squash should be the commit stage.
      */
-    void squash(const Addr &new_PC, const InstSeqNum &seq_num,
-                bool squash_delay_slot, unsigned tid);
+    void squash(const Addr &new_PC, const Addr &new_NPC,
+                const Addr &new_MicroPC,
+                const InstSeqNum &seq_num, unsigned tid);
 
     /** Ticks the fetch stage, processing all inputs signals and fetching
      * as many instructions as possible.
@@ -329,27 +338,24 @@ class DefaultFetch
     /** Wire used to write any information heading to decode. */
     typename TimeBuffer<FetchStruct>::wire toDecode;
 
-    MemObject *mem;
-
     /** Icache interface. */
     IcachePort *icachePort;
 
     /** BPredUnit. */
     BPredUnit branchPred;
 
+    /** Predecoder. */
+    TheISA::Predecoder predecoder;
+
     /** Per-thread fetch PC. */
     Addr PC[Impl::MaxThreads];
 
+    /** Per-thread fetch micro PC. */
+    Addr microPC[Impl::MaxThreads];
+
     /** Per-thread next PC. */
     Addr nextPC[Impl::MaxThreads];
 
-    /** Per-thread next Next PC.
-     *  This is not a real register but is used for
-     *  architectures that use a branch-delay slot.
-     *  (such as MIPS or Sparc)
-     */
-    Addr nextNPC[Impl::MaxThreads];
-
     /** Memory request used to access cache. */
     RequestPtr memReq[Impl::MaxThreads];
 
@@ -361,19 +367,6 @@ class DefaultFetch
     /** Tracks how many instructions has been fetched this cycle. */
     int numInst;
 
-    /** Tracks delay slot information for threads in ISAs which use
-     * delay slots;
-     */
-    struct DelaySlotInfo {
-        InstSeqNum delaySlotSeqNum;
-        InstSeqNum branchSeqNum;
-        int numInsts;
-        Addr targetAddr;
-        bool targetReady;
-    };
-
-    DelaySlotInfo delaySlotInfo[Impl::MaxThreads];
-
     /** Source of possible stalls. */
     struct Stalls {
         bool decode;