* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Kevin Lim
+ * Korey Sewell
*/
#include <limits>
#include <vector>
-#include "sim/root.hh"
+#include "sim/core.hh"
#include "cpu/o3/fu_pool.hh"
#include "cpu/o3/inst_queue.hh"
-using namespace std;
-
template <class Impl>
InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
int fu_idx,
// Set the number of physical registers as the number of int + float
numPhysRegs = numPhysIntRegs + numPhysFloatRegs;
- DPRINTF(IQ, "There are %i physical registers.\n", numPhysRegs);
-
//Create an entry for each physical register within the
//dependency graph.
dependGraph.resize(numPhysRegs);
resetState();
- string policy = params->smtIQPolicy;
+ std::string policy = params->smtIQPolicy;
//Convert string to lowercase
std::transform(policy.begin(), policy.end(), policy.begin(),
maxEntries[i] = part_amt;
}
- DPRINTF(Fetch, "IQ sharing policy set to Partitioned:"
+/*
+ DPRINTF(IQ, "IQ sharing policy set to Partitioned:"
"%i entries per thread.\n",part_amt);
+*/
} else if (policy == "threshold") {
iqPolicy = Threshold;
maxEntries[i] = thresholdIQ;
}
- DPRINTF(Fetch, "IQ sharing policy set to Threshold:"
+/*
+ DPRINTF(IQ, "IQ sharing policy set to Threshold:"
"%i entries per thread.\n",thresholdIQ);
+*/
} else {
assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
"Partitioned, Threshold}");
.name(name() + ".iqSquashedNonSpecRemoved")
.desc("Number of squashed non-spec instructions that were removed")
.prereq(iqSquashedNonSpecRemoved);
-
+/*
queueResDist
.init(Num_OpClasses, 0, 99, 2)
.name(name() + ".IQ:residence:")
for (int i = 0; i < Num_OpClasses; ++i) {
queueResDist.subname(i, opClassStrings[i]);
}
+*/
numIssuedDist
.init(0,totalWidth,1)
.name(name() + ".ISSUE:issued_per_cycle")
//
// How long did instructions for a particular FU type wait prior to issue
//
-
+/*
issueDelayDist
.init(Num_OpClasses,0,99,2)
.name(name() + ".ISSUE:")
;
for (int i=0; i<Num_OpClasses; ++i) {
- stringstream subname;
+ std::stringstream subname;
subname << opClassStrings[i] << "_delay";
issueDelayDist.subname(i, subname.str());
}
-
+*/
issueRate
.name(name() + ".ISSUE:rate")
.desc("Inst issue rate")
.flags(total)
;
issueRate = iqInstsIssued / cpu->numCycles;
-/*
- issue_stores
- .name(name() + ".ISSUE:stores")
- .desc("Number of stores issued")
- .flags(total)
- ;
- issue_stores = exe_refs - exe_loads;
-*/
-/*
- issue_op_rate
- .name(name() + ".ISSUE:op_rate")
- .desc("Operation issue rate")
- .flags(total)
- ;
- issue_op_rate = issued_ops / numCycles;
-*/
+
statFuBusy
.init(Num_OpClasses)
.name(name() + ".ISSUE:fu_full")
template <class Impl>
void
-InstructionQueue<Impl>::setActiveThreads(list<unsigned> *at_ptr)
+InstructionQueue<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
{
- DPRINTF(IQ, "Setting active threads list pointer.\n");
activeThreads = at_ptr;
}
void
InstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr)
{
- DPRINTF(IQ, "Set the issue to execute queue.\n");
- issueToExecuteQueue = i2e_ptr;
+ issueToExecuteQueue = i2e_ptr;
}
template <class Impl>
void
InstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
{
- DPRINTF(IQ, "Set the time buffer.\n");
timeBuffer = tb_ptr;
fromCommit = timeBuffer->getWire(-commitToIEWDelay);
void
InstructionQueue<Impl>::switchOut()
{
+/*
+ if (!instList[0].empty() || (numEntries != freeEntries) ||
+ !readyInsts[0].empty() || !nonSpecInsts.empty() || !listOrder.empty()) {
+ dumpInsts();
+// assert(0);
+ }
+*/
resetState();
dependGraph.reset();
+ instsToExecute.clear();
switchedOut = true;
for (int i = 0; i < numThreads; ++i) {
memDepUnit[i].switchOut();
InstructionQueue<Impl>::resetEntries()
{
if (iqPolicy != Dynamic || numThreads > 1) {
- int active_threads = (*activeThreads).size();
+ int active_threads = activeThreads->size();
+
+ std::list<unsigned>::iterator threads = activeThreads->begin();
+ std::list<unsigned>::iterator end = activeThreads->end();
- list<unsigned>::iterator threads = (*activeThreads).begin();
- list<unsigned>::iterator list_end = (*activeThreads).end();
+ while (threads != end) {
+ unsigned tid = *threads++;
- while (threads != list_end) {
if (iqPolicy == Partitioned) {
- maxEntries[*threads++] = numEntries / active_threads;
+ maxEntries[tid] = numEntries / active_threads;
} else if(iqPolicy == Threshold && active_threads == 1) {
- maxEntries[*threads++] = numEntries;
+ maxEntries[tid] = numEntries;
}
}
}
void
InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx)
{
+ DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum);
// The CPU could have been sleeping until this op completed (*extremely*
// long latency op). Wake it if it was. This may be overkill.
if (isSwitchedOut()) {
+ DPRINTF(IQ, "FU completion not processed, IQ is switched out [sn:%lli]\n",
+ inst->seqNum);
return;
}
int total_issued = 0;
while (total_issued < totalWidth &&
+ iewStage->canIssue() &&
order_it != order_end_it) {
OpClass op_class = (*order_it).queueType;
// complete.
++freeEntries;
count[tid]--;
- issuing_inst->removeInIQ();
+ issuing_inst->clearInIQ();
} else {
memDepUnit[tid].issue(issuing_inst);
}
listOrder.erase(order_it++);
statIssuedInstType[tid][op_class]++;
+ iewStage->incrWb(issuing_inst->seqNum);
} else {
statFuBusy[op_class]++;
fuBusy[tid]++;
unsigned tid = (*inst_it).second->threadNumber;
+ (*inst_it).second->setAtCommit();
+
(*inst_it).second->setCanIssue();
if (!(*inst_it).second->isMemRef()) {
void
InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst)
{
+ DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum);
+ resched_inst->clearCanIssue();
memDepUnit[resched_inst->threadNumber].reschedule(resched_inst);
}
completed_inst->memOpDone = true;
memDepUnit[tid].completed(completed_inst);
-
count[tid]--;
}
// Read instruction sequence number of last instruction out of the
// time buffer.
+#if ISA_HAS_DELAY_SLOT
+ squashedSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
+#else
squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
+#endif
// Call doSquash if there are insts in the IQ
if (count[tid] > 0) {
(squashed_inst->isMemRef() &&
!squashed_inst->memOpDone)) {
+ DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %#x "
+ "squashed.\n",
+ tid, squashed_inst->seqNum, squashed_inst->readPC());
+
// Remove the instruction from the dependency list.
if (!squashed_inst->isNonSpeculative() &&
!squashed_inst->isStoreConditional() &&
++iqSquashedOperandsExamined;
}
- } else {
+ } else if (!squashed_inst->isStoreConditional() ||
+ !squashed_inst->isCompleted()) {
NonSpecMapIt ns_inst_it =
nonSpecInsts.find(squashed_inst->seqNum);
assert(ns_inst_it != nonSpecInsts.end());
+ if (ns_inst_it == nonSpecInsts.end()) {
+ assert(squashed_inst->getFault() != NoFault);
+ } else {
- (*ns_inst_it).second = NULL;
+ (*ns_inst_it).second = NULL;
- nonSpecInsts.erase(ns_inst_it);
+ nonSpecInsts.erase(ns_inst_it);
- ++iqSquashedNonSpecRemoved;
+ ++iqSquashedNonSpecRemoved;
+ }
}
// Might want to also clear out the head of the dependency graph.
// inst will flow through the rest of the pipeline.
squashed_inst->setIssued();
squashed_inst->setCanCommit();
- squashed_inst->removeInIQ();
+ squashed_inst->clearInIQ();
//Update Thread IQ Count
count[squashed_inst->threadNumber]--;
++freeEntries;
-
- DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %#x "
- "squashed.\n",
- tid, squashed_inst->seqNum, squashed_inst->readPC());
}
instList[tid].erase(squash_it--);
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