/*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
#include <map>
#include <queue>
-#include "config/full_system.hh"
-#include "cpu/inst_seq.hh"
#include "cpu/o3/lsq_unit.hh"
+#include "cpu/inst_seq.hh"
#include "mem/port.hh"
#include "sim/sim_object.hh"
+struct DerivO3CPUParams;
+
template <class Impl>
class LSQ {
public:
- typedef typename Impl::Params Params;
typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::DynInstPtr DynInstPtr;
typedef typename Impl::CPUPol::IEW IEW;
};
/** Constructs an LSQ with the given parameters. */
- LSQ(Params *params);
+ LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params);
/** Returns the name of the LSQ. */
std::string name() const;
/** Registers statistics of each LSQ unit. */
void regStats();
- /** Returns dcache port.
- * @todo: Dcache port needs to be moved up to this level for SMT
- * to work. For now it just returns the port from one of the
- * threads.
- */
- Port *getDcachePort() { return &dcachePort; }
-
/** Sets the pointer to the list of active threads. */
- void setActiveThreads(std::list<unsigned> *at_ptr);
- /** Sets the CPU pointer. */
- void setCPU(O3CPU *cpu_ptr);
- /** Sets the IEW stage pointer. */
- void setIEW(IEW *iew_ptr);
+ void setActiveThreads(std::list<ThreadID> *at_ptr);
/** Switches out the LSQ. */
void switchOut();
/** Takes over execution from another CPU's thread. */
void takeOverFrom();
/** Number of entries needed for the given amount of threads.*/
- int entryAmount(int num_threads);
- void removeEntries(unsigned tid);
+ int entryAmount(ThreadID num_threads);
+ void removeEntries(ThreadID tid);
/** Reset the max entries for each thread. */
void resetEntries();
/** Resize the max entries for a thread. */
- void resizeEntries(unsigned size, unsigned tid);
+ void resizeEntries(unsigned size, ThreadID tid);
/** Ticks the LSQ. */
void tick();
/** Ticks a specific LSQ Unit. */
- void tick(unsigned tid)
+ void tick(ThreadID tid)
{ thread[tid].tick(); }
/** Inserts a load into the LSQ. */
/**
* Commits loads up until the given sequence number for a specific thread.
*/
- void commitLoads(InstSeqNum &youngest_inst, unsigned tid)
+ void commitLoads(InstSeqNum &youngest_inst, ThreadID tid)
{ thread[tid].commitLoads(youngest_inst); }
/**
* Commits stores up until the given sequence number for a specific thread.
*/
- void commitStores(InstSeqNum &youngest_inst, unsigned tid)
+ void commitStores(InstSeqNum &youngest_inst, ThreadID tid)
{ thread[tid].commitStores(youngest_inst); }
/**
*/
void writebackStores();
/** Same as above, but only for one thread. */
- void writebackStores(unsigned tid);
+ void writebackStores(ThreadID tid);
/**
* Squash instructions from a thread until the specified sequence number.
*/
- void squash(const InstSeqNum &squashed_num, unsigned tid)
+ void squash(const InstSeqNum &squashed_num, ThreadID tid)
{ thread[tid].squash(squashed_num); }
/** Returns whether or not there was a memory ordering violation. */
* Returns whether or not there was a memory ordering violation for a
* specific thread.
*/
- bool violation(unsigned tid)
+ bool violation(ThreadID tid)
{ return thread[tid].violation(); }
/** Returns if a load is blocked due to the memory system for a specific
* thread.
*/
- bool loadBlocked(unsigned tid)
+ bool loadBlocked(ThreadID tid)
{ return thread[tid].loadBlocked(); }
- bool isLoadBlockedHandled(unsigned tid)
+ bool isLoadBlockedHandled(ThreadID tid)
{ return thread[tid].isLoadBlockedHandled(); }
- void setLoadBlockedHandled(unsigned tid)
+ void setLoadBlockedHandled(ThreadID tid)
{ thread[tid].setLoadBlockedHandled(); }
/** Gets the instruction that caused the memory ordering violation. */
- DynInstPtr getMemDepViolator(unsigned tid)
+ DynInstPtr getMemDepViolator(ThreadID tid)
{ return thread[tid].getMemDepViolator(); }
/** Returns the head index of the load queue for a specific thread. */
- int getLoadHead(unsigned tid)
+ int getLoadHead(ThreadID tid)
{ return thread[tid].getLoadHead(); }
/** Returns the sequence number of the head of the load queue. */
- InstSeqNum getLoadHeadSeqNum(unsigned tid)
+ InstSeqNum getLoadHeadSeqNum(ThreadID tid)
{
return thread[tid].getLoadHeadSeqNum();
}
/** Returns the head index of the store queue. */
- int getStoreHead(unsigned tid)
+ int getStoreHead(ThreadID tid)
{ return thread[tid].getStoreHead(); }
/** Returns the sequence number of the head of the store queue. */
- InstSeqNum getStoreHeadSeqNum(unsigned tid)
+ InstSeqNum getStoreHeadSeqNum(ThreadID tid)
{
return thread[tid].getStoreHeadSeqNum();
}
/** Returns the number of instructions in all of the queues. */
int getCount();
/** Returns the number of instructions in the queues of one thread. */
- int getCount(unsigned tid)
+ int getCount(ThreadID tid)
{ return thread[tid].getCount(); }
/** Returns the total number of loads in the load queue. */
int numLoads();
/** Returns the total number of loads for a single thread. */
- int numLoads(unsigned tid)
+ int numLoads(ThreadID tid)
{ return thread[tid].numLoads(); }
/** Returns the total number of stores in the store queue. */
int numStores();
/** Returns the total number of stores for a single thread. */
- int numStores(unsigned tid)
+ int numStores(ThreadID tid)
{ return thread[tid].numStores(); }
/** Returns the total number of loads that are ready. */
int numLoadsReady();
/** Returns the number of loads that are ready for a single thread. */
- int numLoadsReady(unsigned tid)
+ int numLoadsReady(ThreadID tid)
{ return thread[tid].numLoadsReady(); }
/** Returns the number of free entries. */
unsigned numFreeEntries();
/** Returns the number of free entries for a specific thread. */
- unsigned numFreeEntries(unsigned tid);
+ unsigned numFreeEntries(ThreadID tid);
/** Returns if the LSQ is full (either LQ or SQ is full). */
bool isFull();
* Returns if the LSQ is full for a specific thread (either LQ or SQ is
* full).
*/
- bool isFull(unsigned tid);
+ bool isFull(ThreadID tid);
/** Returns if any of the LQs are full. */
bool lqFull();
/** Returns if the LQ of a given thread is full. */
- bool lqFull(unsigned tid);
+ bool lqFull(ThreadID tid);
/** Returns if any of the SQs are full. */
bool sqFull();
/** Returns if the SQ of a given thread is full. */
- bool sqFull(unsigned tid);
+ bool sqFull(ThreadID tid);
/**
* Returns if the LSQ is stalled due to a memory operation that must be
* Returns if the LSQ of a specific thread is stalled due to a memory
* operation that must be replayed.
*/
- bool isStalled(unsigned tid);
+ bool isStalled(ThreadID tid);
/** Returns whether or not there are any stores to write back to memory. */
bool hasStoresToWB();
/** Returns whether or not a specific thread has any stores to write back
* to memory.
*/
- bool hasStoresToWB(unsigned tid)
+ bool hasStoresToWB(ThreadID tid)
{ return thread[tid].hasStoresToWB(); }
/** Returns the number of stores a specific thread has to write back. */
- int numStoresToWB(unsigned tid)
+ int numStoresToWB(ThreadID tid)
{ return thread[tid].numStoresToWB(); }
/** Returns if the LSQ will write back to memory this cycle. */
/** Returns if the LSQ of a specific thread will write back to memory this
* cycle.
*/
- bool willWB(unsigned tid)
+ bool willWB(ThreadID tid)
{ return thread[tid].willWB(); }
/** Returns if the cache is currently blocked. */
bool cacheBlocked()
- { return retryTid != -1; }
+ { return retryTid != InvalidThreadID; }
/** Sets the retry thread id, indicating that one of the LSQUnits
* tried to access the cache but the cache was blocked. */
- void setRetryTid(int tid)
+ void setRetryTid(ThreadID tid)
{ retryTid = tid; }
/** Debugging function to print out all instructions. */
void dumpInsts();
/** Debugging function to print out instructions from a specific thread. */
- void dumpInsts(unsigned tid)
+ void dumpInsts(ThreadID tid)
{ thread[tid].dumpInsts(); }
- /** Executes a read operation, using the load specified at the load index. */
- template <class T>
- Fault read(RequestPtr req, T &data, int load_idx);
+ /** Executes a read operation, using the load specified at the load
+ * index.
+ */
+ Fault read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
+ uint8_t *data, int load_idx);
/** Executes a store operation, using the store specified at the store
- * index.
+ * index.
*/
- template <class T>
- Fault write(RequestPtr req, T &data, int store_idx);
+ Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
+ uint8_t *data, int store_idx);
- /** DcachePort class for this LSQ. Handles doing the
- * communication with the cache/memory.
+ /**
+ * Retry the previous send that failed.
*/
- class DcachePort : public Port
- {
- protected:
- /** Pointer to LSQ. */
- LSQ *lsq;
-
- public:
- /** Default constructor. */
- DcachePort(LSQ *_lsq)
- : lsq(_lsq)
- { }
-
- protected:
- /** Atomic version of receive. Panics. */
- virtual Tick recvAtomic(PacketPtr pkt);
-
- /** Functional version of receive. Panics. */
- virtual void recvFunctional(PacketPtr pkt);
-
- /** Receives status change. Other than range changing, panics. */
- virtual void recvStatusChange(Status status);
-
- /** Returns the address ranges of this device. */
- virtual void getDeviceAddressRanges(AddrRangeList &resp,
- AddrRangeList &snoop)
- { resp.clear(); snoop.clear(); }
-
- /** Timing version of receive. Handles writing back and
- * completing the load or store that has returned from
- * memory. */
- virtual bool recvTiming(PacketPtr pkt);
-
- /** Handles doing a retry of the previous send. */
- virtual void recvRetry();
- };
+ void recvRetry();
- /** D-cache port. */
- DcachePort dcachePort;
+ /**
+ * Handles writing back and completing the load or store that has
+ * returned from memory.
+ *
+ * @param pkt Response packet from the memory sub-system
+ */
+ bool recvTiming(PacketPtr pkt);
+
+ /** The CPU pointer. */
+ O3CPU *cpu;
+
+ /** The IEW stage pointer. */
+ IEW *iewStage;
protected:
/** The LSQ policy for SMT mode. */
/** The LSQ units for individual threads. */
LSQUnit thread[Impl::MaxThreads];
- /** The CPU pointer. */
- O3CPU *cpu;
-
- /** The IEW stage pointer. */
- IEW *iewStage;
-
/** List of Active Threads in System. */
- std::list<unsigned> *activeThreads;
+ std::list<ThreadID> *activeThreads;
/** Total Size of LQ Entries. */
unsigned LQEntries;
unsigned maxSQEntries;
/** Number of Threads. */
- unsigned numThreads;
+ ThreadID numThreads;
/** The thread id of the LSQ Unit that is currently waiting for a
* retry. */
- int retryTid;
+ ThreadID retryTid;
};
template <class Impl>
-template <class T>
Fault
-LSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
+LSQ<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
+ uint8_t *data, int load_idx)
{
- unsigned tid = req->getThreadNum();
+ ThreadID tid = req->threadId();
- return thread[tid].read(req, data, load_idx);
+ return thread[tid].read(req, sreqLow, sreqHigh, data, load_idx);
}
template <class Impl>
-template <class T>
Fault
-LSQ<Impl>::write(RequestPtr req, T &data, int store_idx)
+LSQ<Impl>::write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
+ uint8_t *data, int store_idx)
{
- unsigned tid = req->getThreadNum();
+ ThreadID tid = req->threadId();
- return thread[tid].write(req, data, store_idx);
+ return thread[tid].write(req, sreqLow, sreqHigh, data, store_idx);
}
#endif // __CPU_O3_LSQ_HH__
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