cpu, arch, arch-arm: Wire unused VecElem code in the O3 model

[gem5.git] / src / cpu / o3 / rename_map.hh

diff --git a/src/cpu/o3/rename_map.hh b/src/cpu/o3/rename_map.hh
index ab909f0902971dc0338cfb6299ed10b369540bcb..d30668027d258f61772b6e8c57b485c787638117 100644 (file)
--- a/src/cpu/o3/rename_map.hh
+++ b/src/cpu/o3/rename_map.hh
@@ -160,7 +160,6 @@ class SimpleRenameMap
     /** @} */
 };
 
-
 /**
  * Unified register rename map for all classes of registers.  Wraps a
  * set of class-specific rename maps.  Methods that do not specify a
@@ -377,8 +376,16 @@ class UnifiedRenameMap
     /**
      * Set vector mode to Full or Elem.
      * Ignore 'silent' modifications.
+     *
+     * @param newVecMode new vector renaming mode
+     */
+    void switchMode(VecMode newVecMode);
+
+    /**
+     * Switch freeList of registers from Full to Elem or vicevers
+     * depending on vecMode (vector renaming mode).
      */
-    void switchMode(VecMode newVecMode, UnifiedFreeList* freeList);
+    void switchFreeList(UnifiedFreeList* freeList);
 
 };