/*
- * Copyright (c) 2010-2012 ARM Limited
+ * Copyright (c) 2010-2012, 2016-2017 ARM Limited
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* Korey Sewell
*/
+#ifndef __CPU_O3_THREAD_CONTEXT_IMPL_HH__
+#define __CPU_O3_THREAD_CONTEXT_IMPL_HH__
+
#include "arch/kernel_stats.hh"
#include "arch/registers.hh"
#include "config/the_isa.hh"
void
O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
{
- // some things should already be set up
- assert(getSystemPtr() == old_context->getSystemPtr());
- assert(getProcessPtr() == old_context->getProcessPtr());
-
- // copy over functional state
- setStatus(old_context->status());
- copyArchRegs(old_context);
- setContextId(old_context->contextId());
- setThreadId(old_context->threadId());
+ ::takeOverFrom(*this, *old_context);
+ TheISA::Decoder *newDecoder = getDecoderPtr();
+ TheISA::Decoder *oldDecoder = old_context->getDecoderPtr();
+ newDecoder->takeOverFrom(oldDecoder);
- if (FullSystem) {
- EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
- if (other_quiesce) {
- // Point the quiesce event's TC at this TC so that it wakes up
- // the proper CPU.
- other_quiesce->tc = this;
- }
- if (thread->quiesceEvent) {
- thread->quiesceEvent->tc = this;
- }
-
- // Transfer kernel stats from one CPU to the other.
- thread->kernelStats = old_context->getKernelStats();
- cpu->lockFlag = false;
- } else {
- thread->funcExeInst = old_context->readFuncExeInst();
- }
-
- old_context->setStatus(ThreadContext::Halted);
+ thread->kernelStats = old_context->getKernelStats();
+ thread->funcExeInst = old_context->readFuncExeInst();
thread->noSquashFromTC = false;
thread->trapPending = false;
template <class Impl>
void
-O3ThreadContext<Impl>::activate(Cycles delay)
+O3ThreadContext<Impl>::activate()
{
DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
threadId());
thread->setStatus(ThreadContext::Active);
// status() == Suspended
- cpu->activateContext(thread->threadId(), delay);
+ cpu->activateContext(thread->threadId());
}
template <class Impl>
void
-O3ThreadContext<Impl>::suspend(Cycles delay)
+O3ThreadContext<Impl>::suspend()
{
DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
threadId());
if (thread->status() == ThreadContext::Suspended)
return;
+ if (cpu->isDraining()) {
+ DPRINTF(O3CPU, "Ignoring suspend on TC due to pending drain\n");
+ return;
+ }
+
thread->lastActivate = curTick();
thread->lastSuspend = curTick();
template <class Impl>
void
-O3ThreadContext<Impl>::halt(Cycles delay)
+O3ThreadContext<Impl>::halt()
{
- DPRINTF(O3CPU, "Calling halt on Thread Context %d\n",
- threadId());
+ DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", threadId());
if (thread->status() == ThreadContext::Halted)
return;
O3ThreadContext<Impl>::regStats(const std::string &name)
{
if (FullSystem) {
- thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
+ thread->kernelStats = new TheISA::Kernel::Statistics();
thread->kernelStats->regStats(name + ".kern");
}
}
-template <class Impl>
-void
-O3ThreadContext<Impl>::serialize(std::ostream &os)
-{
- if (FullSystem && thread->kernelStats)
- thread->kernelStats->serialize(os);
-}
-
-template <class Impl>
-void
-O3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string §ion)
-{
- if (FullSystem && thread->kernelStats)
- thread->kernelStats->unserialize(cp, section);
-}
-
template <class Impl>
Tick
O3ThreadContext<Impl>::readLastActivate()
}
template <class Impl>
-TheISA::FloatReg
-O3ThreadContext<Impl>::readFloatRegFlat(int reg_idx)
+TheISA::FloatRegBits
+O3ThreadContext<Impl>::readFloatRegBitsFlat(int reg_idx)
{
- return cpu->readArchFloatReg(reg_idx, thread->threadId());
+ return cpu->readArchFloatRegBits(reg_idx, thread->threadId());
}
template <class Impl>
-TheISA::FloatRegBits
-O3ThreadContext<Impl>::readFloatRegBitsFlat(int reg_idx)
+const TheISA::VecRegContainer&
+O3ThreadContext<Impl>::readVecRegFlat(int reg_id) const
+{
+ return cpu->readArchVecReg(reg_id, thread->threadId());
+}
+
+template <class Impl>
+TheISA::VecRegContainer&
+O3ThreadContext<Impl>::getWritableVecRegFlat(int reg_id)
{
- return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
+ return cpu->getWritableArchVecReg(reg_id, thread->threadId());
+}
+
+template <class Impl>
+const TheISA::VecElem&
+O3ThreadContext<Impl>::readVecElemFlat(const RegIndex& idx,
+ const ElemIndex& elemIndex) const
+{
+ return cpu->readArchVecElem(idx, elemIndex, thread->threadId());
+}
+
+template <class Impl>
+TheISA::CCReg
+O3ThreadContext<Impl>::readCCRegFlat(int reg_idx)
+{
+ return cpu->readArchCCReg(reg_idx, thread->threadId());
}
template <class Impl>
template <class Impl>
void
-O3ThreadContext<Impl>::setFloatRegFlat(int reg_idx, FloatReg val)
+O3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, FloatRegBits val)
{
- cpu->setArchFloatReg(reg_idx, val, thread->threadId());
+ cpu->setArchFloatRegBits(reg_idx, val, thread->threadId());
conditionalSquash();
}
template <class Impl>
void
-O3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, FloatRegBits val)
+O3ThreadContext<Impl>::setVecRegFlat(int reg_idx, const VecRegContainer& val)
{
- cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
+ cpu->setArchVecReg(reg_idx, val, thread->threadId());
conditionalSquash();
}
template <class Impl>
void
-O3ThreadContext<Impl>::pcState(const TheISA::PCState &val)
+O3ThreadContext<Impl>::setVecElemFlat(const RegIndex& idx,
+ const ElemIndex& elemIndex, const VecElem& val)
{
- cpu->pcState(val, thread->threadId());
+ cpu->setArchVecElem(idx, elemIndex, val, thread->threadId());
+ conditionalSquash();
+}
+
+template <class Impl>
+void
+O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, TheISA::CCReg val)
+{
+ cpu->setArchCCReg(reg_idx, val, thread->threadId());
conditionalSquash();
}
template <class Impl>
void
-O3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val)
+O3ThreadContext<Impl>::pcState(const TheISA::PCState &val)
{
cpu->pcState(val, thread->threadId());
}
template <class Impl>
-int
-O3ThreadContext<Impl>::flattenIntIndex(int reg)
+void
+O3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val)
{
- return cpu->isa[thread->threadId()]->flattenIntIndex(reg);
+ cpu->pcState(val, thread->threadId());
+
+ conditionalSquash();
}
template <class Impl>
-int
-O3ThreadContext<Impl>::flattenFloatIndex(int reg)
+RegId
+O3ThreadContext<Impl>::flattenRegId(const RegId& regId) const
{
- return cpu->isa[thread->threadId()]->flattenFloatIndex(reg);
+ return cpu->isa[thread->threadId()]->flattenRegId(regId);
}
template <class Impl>
conditionalSquash();
}
+#endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__
template <class Impl>
void
O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)